DDR single bit fault detected by ecc

[debduttabanerje]

Getting DDR "Faulty Data bit: 33" error reported by EDAC. T1022 based custom board. 8GB DDR4 DIMM from Apacer

No error in ddr initialization in uboot and mtest runs successfully. (see log: uboot_log_mtest.txt)

As per discussions on similar problems here, tried the qcvs ddr validation.

Here is the process I followed: (codewarior-10.5.1 for PA)

Used SPD based configuration in QCVS DDR setup (cngs_val_4.png)

Now performed the centering the clock test scenario write-read-compare test with 1 repetition.

But not getting any green cells in the results. All are orange. ACE error in DDR_ERR_DETECT reg.

Please see attached pic: cngs_val_2.png

Also one output text log: test_optimized_clock_centering_segm_A_2_8_.log

What may be wrong with this board?

kindly give us some direction to where to look next.

T1042

[yipingwang]

Please check include/configs/T104xRDB.h in your u-boot source code, whether "SPD_EEPROM_ADDRESS" is defined as "0x51".

When connecting to the target board, the CCS(CodeWarrior Connection Server) will pop up, you could type “log v” in the CCS console, then connect to the target board again to capture the low level CCS log to me to do more investigation.

[debduttabanerje]

Sorry for the delayed response.

1. verified that SPD_EEPROM_ADDRESS is set as 0x51 in include/configs/T104xRDB.h

2. attached the log (debug.txt) from CCS(CodeWarrior Connection Server)

[yipingwang]

Please try the following method.

Please create a CodeWarrior bare board project following new project wizards in CodeWarrior IDE, please select "Attach" launch configuration in Debug Target Settings panel.

After setting up u-boot on your target board, please connect CodeWarrior to your target board from Run->Debug Configurations-><project>-core00_RAM_T1022_Attach->Debug.

Then open reading registers panel from Window->Show View->Other->Debug->Registers, please copy and save DDR controller registers.

In the QCVS DDRv project, please export DDR controller registers to a .regs file, please compare these registers values with the setting captured with CodeWarror, and modify register values setting in the .regs file and import it back to the QCVS project.

[debduttabanerje]

Hi,

Please accept our apologies for very delayed response. The code warrior tool was not available.

As per your advice setup a bareboard project with "attach" launch configuration. The ddr controller register was copied (attached).

But the dump format doesn't match with with register export format from qcvs.

Anyway after comparison and modification imported back the registers. and again started validation.

However the result is same.

Now u-boot is stuck where u-boot is copied from spi flash to ddr. (attached)

[debduttabanerje]

Dear NXP team,

eagerly awaiting for response.

[yipingwang]

Would you please create a new thread to discuss your current problem?

The original case has already closed in our system.