I’m having problems running the CodeWarrior Validation tool on custom hardware, i am using T2081 Based Board.
Problem : We are using discrete DDR3 (MT41K128M16JT-125 XIT:K) 32bit Bus and DDR data rate configured 1066 MT/s in the RCW
and QCVS DDR tool but getting Errors in Code Warrior Validation Tool
"Exception: (<<Core interrupted by exception: Machine check interrupt!>>)" and
"Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware".
For Configuration of DDR3 in QCVS DDR tool i am using Data Sheet of the DDR3 and Application Note "AN4039"
System Clock (SCLK) is set to 66.66MHz and Memory Clock (DDRCLK) is set to 133.33MHz on the Processor Properties page.
For Configuration i am using Code Warrior v10.5.1.
Please check the below error logs from Code warrior.
I don't know what is causing the problem.
Help me in resolving this issue.
Thanks & Regards,
Hello nshul Khare,
First of all regarding how to use QCVS DDRv tool, if there is no SPD on your target board, please create a QCVS DDR project with the default configuration, then modify DDR Properties panel according to your DDR data sheet, please make sure the related frequency configuration in DDRv project is the same as the target board.
I checked registers values captured you, it seems they were not the real status when the error occurred. If the error "D_INIT was not cleared by hardware" occurs, as usual ACE bit of DDR_ERR_DETECT(0x00008E40) should be set. Would you please refer to the following procedure to capture the CCS console log to me?
When you use DDRv tool to connect to the target board, CodeWarrior connection Sever will be invoked automatically, please open it at the right bottom of the task bar, then type command "log v" in CCS console. In CodeWarrior IDE, please connect to the target board again, the low level communication log between DDRv and the target board will be captured in the CCS console, please click "Start Validation", then capture the CCS log and send it to me to do more investigation.
If DDR_ERR_DETECT[ACE] is set, the following is the proper reason.