CodeWarrior DDR tool - DDR Initialization failed: D_INIT was not cleared - Tests not executed

[erik_pet]

We have been having significant issues with getting the CodeWarrior DDR Validation tool to run the tests on our custom t2080 board.

Initially we were having connection issues with attaching to the target, however once lowering the JTAG speed down from the expected 33333K to 2K we have been able to establish a connection.

With this connection we have run the full set of tests several times, with a failed/untested result on every occasion. The logs for each test run indicate that the Test was not executed and has each test has yielded an orange “Configuration Error” result for every value tested.

The specific errors identified on every test are:

Run 1: “Error configuring the target! – DDR initialization failed: D_INIT was not cleared by the hardware!”

Run 2: “ERR_DETECT register is not empty, test did not run.”

Run 3: “ERR_DETECT register is not empty, test did not run.”

The full log for a single test failure is attached, but this is mostly identical to the output for each test.

The DDR component properties has been configured according to the datasheet of the ram being used, along with the specifics of our board. Steps have been taken to confirm the integrity of the RCW, bit by bit, as well as testing with modified DDR bus clock values with no success.

We had also shortened the connection between the CWTAP device and the board to remove the possibility of signal integrity loss, however this did not produce any difference.

Please let me know if I can provide any more specifics about the issues we have been seeing, or information about the board/RAM used. We are using CodeWarrior v 10.5.1 with QVCS installation package installed.

We are at a bit of a standstill as most of the ideas we have had to get these tests yielding results have been exhausted.

Thank you for your time any guidance you can provide,

Erik

[yipingwang]

DDR Bring up HW checklist:
Schematics review
Design checklist document
Layout/HW guideline application note AN5097

HW specs
Check all voltages: GVDD, VREF, VTT, AND VPP
Check input and output DDR clocks
Verify DRAM reset signal is matched to HRESET for UDIMM,
SoDIMM, and discrete DRAM. AN5097 appendix B.
Verify correct DRAM type strap
Verify DQ pin swapping is per allowed limitation
Have more than one board for bring up
Check for manufacturing/fabrication/assembly issues

DDR Bring up SW checklist:
Generate the setting via QCVS
Use SPD if available, otherwise Auto generation
Select the DDR data rate based on the measured output clock
RCW needs to be valid and correct
Enter MCK to DQS skews in the DDR wizard
Verify the DQn_MAP registers are correct