Hi,
MMA9555L use Coldfire V1 core.
The I2C block is a common I2C block and used by many NXP devices.
Please see AN3464 which has some good example code on how to use the I2C block as a master device.
http://www.freescale.com/files/32bit/doc/app_note/AN3464.pdf
Specifically:
Figure 8A. Code Snippet for Initializing the IIC Module in the V1 MC51QExx Processor
Figure 9A. Code Snippet Showing How to Send a Byte Over the IIC Bus Using the MC51QEx Processor
Figure 10A. Code Snippet Showing How to Receive a Byte Over the IIC Bus Using the MC51QEx Processor
Please note that the register names are not exactly the same, but with the MMA955x register header files and the
MMA955x hardware reference manual, it is easy enough to adjust. The App Note uses register name conventions which include a number to indicate which peripheral is being accessed, some processors can have multiple I2C peripheral blocks. The MMA955x only has the one I2C master block, so this number has been removed in the MMA955x register header files. Due to the “I”s and “1”s in various combinations, this is actually a significant source or problems when porting drivers to the MMA955x.
For example:
APP Note convention = MMA955x Convention
IIC1F = IICF
IIC1S = IICS
IIC1C1 = IICC1
IIC1C1_IICEN = IICC1_IICEN
I hope that this helps.
Have a great day,
Jennie Zhang
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