Problem with Interrupts MC9S12XDP512

[Claire]

Hello,

I would like to have 4 signals in output in same time.

I use 4 interrupts that uses timer-counter.

But when I see t 4 output, just one interrupt run correctly (interrupt 2). I think I have a problem with priority (normally I desable all)

I don't understand why I have only one signal correctly  instead of 4.

Thank you,

Original Attachment has been moved to: main02-13.c.zip

[Claire]

In SK-S12XDP512-A 's schematic, it's PT1 that read correctly.

Why PT0, PT2 and PT3 are don't read like PT1, in a same time ?

[RadekS]

I shortly checked your code and I have few points for you:

1. DDRT = 0X0F; I would like to recommend DDRT = 0x0F;
2. I don’t see initialization of TCx registers. You write there only in interrupt routine. I would like to recommend set ECT registers (Include TCx register) inside timer_counter() function.
3. Default priority level is 1, if you don’t change, interrupts routines will be serviced subsequently. If there is more pending interrupts with the same priority in the same time. Interrupt at higher interrupt vector wins.
4. Commands like INT_CFDATA0 = 0x00; doesn’t have any sense here. If you want disable interrupt for any timer channel, please use TIE register.
5. If you want change priority, you have to set INT_CFADDR and after that modify some of INT_CFDATAx registers. Example Code:

#define ECT0_VEC  0xEE /* vector address= 2 * channel id */

#define CHANGE_PRIORITY(vec_adr, cfdata)                \

  INT_CFADDR= (vec_adr) & 0xF0; \

INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)

CHANGE_PRIORITY (ECT0_VEC, 0x05); /* RQST=0 and PRIO=5 */

[Claire]

Ok

And if I want a same priority for the four interrupts. It's the same code or I must write for interrupt 2 (for exemple):

#define ECT1_VEC  0xEE /* vector address= 2 * channel id */

#define CHANGE_PRIORITY(vec_adr, cfdata)                \

  INT_CFADDR= (vec_adr) & 0xF0; \

INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)

CHANGE_PRIORITY (ECT1_VEC, 0x05); /* RQST=0 and PRIO=5 */

.....

Or is it possible to desable all priority ? Because, for me, TIE enable interrupt but doesn't control priorities.

For change vector adress why 0xEE means 2 ?

I don't understand your code. What does it mean ?

What is vec_adr and cfdata ? they are integers ?

[RadekS]

There are 120 interrupt vectors. For saving occupied register space, priority registers are accessible trough “page” CFADDR. Interrupt vectors are divided into groups of eight vectors (CFDATA0..CFDATA7).

This way we can set priority for almost all interrupts by 9 registers.

#define ECT0_VEC  0xEE

This definition just contains lower part of interrupt vector address. See Table 1-12. Interrupt Vector Locations in RM (page 73..75).

Similar way we can define other vectors:

#define ECT0_VEC  0xEE

#define ECT1_VEC  0xEC

#define ECT2_VEC  0xEA

#define ECT3_VEC  0xE8

CHANGE_PRIORITY(vec_adr, cfdata) is just universal function for priority change (and route to XGATE when RQST=1) where vec_adr is vector address from previous definitions and cfdata is content which we want write into appropriate CFDATAx register.

Into INT_CFADDR we write just higher half-byte from vector address, in all our cases 0xE.

Vectors contains 16bit addresses, therefore we take lower part from vector address and divide by 2 (shift to right >> 1). For example: ECT3_VEC  0xE8, we take 0x8, divide by two is 0x4, therefore we write into CFDATA4

We should call this function for every vector (where we want change priority/route to XGATE)

For example:

CHANGE_PRIORITY (ECT0_VEC, 0x05); /* RQST=0 and PRIO=5 */

CHANGE_PRIORITY (ECT1_VEC, 0x04); /* RQST=0 and PRIO=4 */

CHANGE_PRIORITY (ECT2_VEC, 0x01); /* RQST=0 and PRIO=1 */

CHANGE_PRIORITY (ECT3_VEC, 0x87); /* routed to XGATE RQST=1 and PRIO=7 */   

[Claire]

Ok

So if I want write into CFDATA1, I take ECT2_VEC 0xE2 ?

And if I want the same priority for 4 interrupts without XGATE I can write :

CHANGE_PRIORITY (ECT0_VEC, 0x05);

CHANGE_PRIORITY (ECT1_VEC, 0x05);

CHANGE_PRIORITY (ECT2_VEC, 0x05);

CHANGE_PRIORITY (ECT3_VEC, 0x05);   

In this code I will modify like this :

#define ECT0_VEC  0xE1 /* vector address= 2 * channel id */

#define ECT1_VEC  0xE2/* vector address= 2 * channel id */

#define ECT2_VEC  0xE4/* vector address= 2 * channel id */

#define ECT3_VEC  0xE6/* vector address= 2 * channel id */

#define CHANGE_PRIORITY(vec_adr, cfdata)

INT_CFADDR= (vec_adr) & 0xF0; \

INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)

CHANGE_PRIORITY (ECT0_VEC, 0x05); /* RQST=0 and PRIO=5 */

CHANGE_PRIORITY (ECT1_VEC, 0x05); /* RQST=0 and PRIO=5 */

CHANGE_PRIORITY (ECT2_VEC, 0x05); /* RQST=0 and PRIO=5 */

CHANGE_PRIORITY (ECT3_VEC, 0x05); /* RQST=0 and PRIO=5 */

[RadekS]

No, you cannot define ECT1_VEC  as 0xE2. Vector address 0xE2 refers to ECT channel 6. Please look at Table 1-12. Interrupt Vector Locations in RM (page 73..75).

You will see that ECT channel 0 has vector address 0xEE (0xFFEE in default state of IVBR register).

#define ECT0_VEC  0xEE

#define ECT1_VEC  0xEC

#define ECT2_VEC  0xEA

#define ECT3_VEC  0xE8

[Claire]

Yes, I see.

But you say :

For example: ECT3_VEC  0xE8, we take 0x8, divide by two is 0x4, therefore we write into CFDATA4

So I think if I take ECT1_VEC 0xE2, I write into CFDATA1.

I just tested the new code but interrpts don't run correctly. I send frame in Bus CAN and when I modify data, the signal at in output does not change. (I must have 4 slot signals based on the input data). Only 1 interrupt run correctly (TOC1_ISR)

[RadekS · Accepted solution]

Yes, with one exception:

“I take ECT6_VEC 0xE2, I write into CFDATA1”

Back to your code:

Did you test that all your wheel_ arrays contain correct data (if you received correct data over CAN)?

Can you put breakpoint into TC0 (for example) interrupt routine and test if CPU executes this code?

Are you sure that you watch correct pins (connector J101, pins 11..14)?

[Claire]

Thank you. I don't but I had an error when I write in my buffer. When I put a breakpoint I see this error.

But just last question,TCO run correctly only when i send data upper than 0xDD and haven't the same period as the other signals.

Join frame captur with data = 0xCC, data = 0xDD and screen printed of CANalyzer' interactive generator block.