FreeCntr - I don't understand the period parameter

[robertp]

Hello,

I am running on a MC9S12C64 at 8Mhz.

I am trying to use a FreeCntr and am having trouble with a couple of items.  First is the "period" parameter in the configuration.  What does it mean?  If i go into the timer configuration, I can manually set the prescaler, which will change how fast the timer counts and therefore, how quickly it overflows.  I have verified this with a scope - if I set the prescaler to 1, the overflow interrupt will occur every 16.384ms.  If I set the prescaler to 2, the overflow interrupt will occur every 32.768ms.  But what is the "period" parameter for - what does it do, why/how do I use it? 

Also once the interrupt is triggered, is there a way to tell if the interrupt is due to a Compare or an Overflow?

What I am attempting to do is use the freeCntr and the Compare function.  I know that my compare interval is always less than the overflow time (e.g. if prescaler is 1, I know the compare interval is always less than 16.3ms).  This allows me to let the compare wrap around when I do the addition:

short val;
GetCounterValue(&val);
compareVal = val + compareInterval;
SetCompare(compareVal);

here, I KNOW that the sum of val and compareInterval might overflow, but that is OK, the total time is still accurate: i.e.,  the interval from 16383 to 9 is 10us, just as the interval from 0 to 10 is 10us, it just so happens that in the former, there was a counter overflow.

The problem is, in the interrupt service routine, how do I ignore the counter overflow interrupt and only handle the Compare interrupt.

[robertp]

correction - overflow of the counter register, of course, is at 65536, NOT 16384.  If the prescaler is at 1, the overflow interrupt is every 16.3ms because the clock is running at 4Mhz.  To get one microsecond, I set the prescaler to 4 and then overflow occurs at 65.5ms.   Other than this timing correction, the rest of my question still remains.

[ProcessorExpert]

I am not sure what you do need exactly to do. But, if you need to generate the periodic interrupt it's better to use the "TimerInt" bean. Is there any reason why you could not to use the "TimerInt" bean?

Anyway, period is the time before re-initialization of a counter. The way to tell if the interrupt is due to a Compare or an Overflow is through the "Reset Counter on Compare" property.
  - If the property is set to "yes", counter is reset each time when compare matches the counter value.
(On the MC9S12C64 CPU the "yes" value is possible to set only if the the "TC7" value in the "Device" property is set.)
  - If the property is set to "no", counter is reset each time when the counter overflows.

More information and an example of typical usage you can find in the "Help" of the bean. You find it in the pop-up menu of the bean.

It's also not clear which PE version do you use. However, I recommend to update to the latest version of Processor Expert (PE 2.98 for CW 4.6).

[robertp]

What I am trying to do is an outputCompare initiated by trigger interrupt - one pulse into the micro generates an interrupt which I use to set up an output pulse using an outputCompare. I spent some additional time reviewing the hardware timer module documentation and now understand that the outputCompare interrupt and the overflow interrupt are completely separate interrupts - that is not clear from the bean documentation.

On the issue of period - your response is the same statement that is in the documentation: period is the time before re-initialization of a counter. But what does that MEAN? "before re-initialization", but AFTER WHAT? what triggers the "re-initialization"

Thanks

[ProcessorExpert · Accepted solution]

Meaning of the time in the "Period" property depends on selected device type and "Reset on counter compare" property.

For free-running devices or if "Reset on compare" property is selected, the time in this property represent interrupt period.

Otherwise (for compare devices and "Reset counter on compare" property is set to "no" ) the time in this property represent offset (delay) between counter overflow and interrupt invocation. In this case interrupt period is defined by timer overflow.