Buffered and Non-buffered uart ioctl

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Buffered and Non-buffered uart ioctl

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pgillaspy
Contributor III

Running bare metal software on MC56F800-EVK with CW11.1 and DSC Quickstart 2.7.

Two questions:

(1)  When reading uart in buffered mode and using ioctl(SCI0, SCI_GET_RX_CHARS_READY, NULL) to determine how many chars are in read buffer, the ioctl always returns 1 (even when there is no input).  Why?

(2) When reading uart in non-buffered mode, there appears to be no ioctl call to determine if a char is in the read data register. There appears to be no way to determine if a char has been received. Am I wrong?

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pgillaspy
Contributor III

I got the SCI successfully running without using buffered IO. i am using non-buffered but with the TX and RX FIFOs enabled. By carefully reading the tech manual, I was able to setup the TX FIFO full count and the RX FIFO empty count flags such that I am able to TX and RX  very efficiently. Consider this support item closed.

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xiangjun_rong
NXP TechSupport
NXP TechSupport
Hi, Q1)When reading uart in buffered mode and using ioctl(SCI0, SCI_GET_RX_CHARS_READY, NULL) to determine how many chars are in read buffer, the ioctl always returns 1 (even when there is no input). Why? >>>>>>pls check the body of api function ioctl(SCI0, SCI_GET_RX_CHARS_READY, NULL), and check how the driver code to read data from receiver register to the buffer. (2) When reading uart in non-buffered mode, there appears to be no ioctl call to determine if a char is in the read data register. There appears to be no way to determine if a char has been received. Am I wrong? >>>>>Can you tell us the DSC part number? Anyway, I suppose that you use interrupt mode, as you know that there is FIFO for the SCI receiver, in the ISR of receiver, you can check the QSCI Control Register 2 (QSCIx_CTRL2), the QSCIx_CTRL2[RFCNT] bits represent the number of bytes the SCI has received. You can check the bits in ISR and read the data from FIFO. Hope it can help you BR XiangJun Rong 10–8 RFCNT Receive FIFO Count These read only bits show how many words are used in the RX FIFO. As words are received, CTRL2[RFCNT] is incremented. As words are read from DATA the value of CTRL2[RFCNT] decrements. There is one word time to read DATA between when STAT[RDRF] is set (interrupt asserted), due to the RX FIFO being full, and when an overflow condition is flagged. 000 0 words in RX FIFO 001 1 word in RX FIFO 010 2 words in RX FIFO 011 3 words in RX FIFO 100 4 words in RX FIFO 101 Reserved 110 Reserved 111 Reserved
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