Increase in PMIC VDD prior to each core voltage reduction: Dynamic Voltage Scaling with i.MX RT500

[richard_mcpartland]

Thanks for an interesting video/article Dynamic Voltage Scaling with i.MX RT500 PVT Sensor.

One question... why does the PMIC voltage jump up ~30mV prior to each Vcore reduction?

[dereksnell]

Hi @richard_mcpartland ,

Thank you for your question.  This is a behavior of the PCA9420 PMIC.  We are working with the PMIC team to provide more details about it for you.

Best regards

[jrrlopez]

Hi @richard_mcpartland,

This is Juan from the NXP PMIC team. My colleague @dereksnell involved me on this topic.

To answer your question, the behavior seen on the PCA9420 is related with a temporary internal voltage reference shift when the SW1 output transitions from one voltage to the other. It is related with the active discharge circuit being enabled and whenever the target voltage is changed, the internal new target reference voltage goes through a temporary voltage reference shift causing this spike. This behavior can be removed by disabling the active discharge on SW1 on PCA9420 via an IIC command. The only consequence here is that SW1 will basically discharge depending on the MCU's current load but this is even a better power efficient solution since no more power is burned through the internal discharge resistor on our PCA9420.

Let us know please whether this clarifies your question.

Thanks,

Juan