writing to internal Flash and interrupt latency

[Potatoswatter]

While writing to or erasing the Flash memory on an HCS08 or ColdFire v1 Flexis MCU, read accesses are illegal and return invalid data. Assuming all ISRs are in Flash, no interrupts may be serviced while Flash is writing or erasing. This takes up to 20 ms, which is a bit long.

Is there a way to abort a Flash command in progress (FSTAT_FCCF = 0) such that read access is restored? It appears the user manuals for the MC9S08MP16 and the MCF51JM128 differ slightly in wording:

MC9S08MP16RM §4.5.5: Any of the following actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.

MCF51JM128RM §4.5.3.1: The FACCERR flag is set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort:

According to the manuals, the ColdFire Flexis part immediately aborts a write if I write to any Flash register while a command is in progress, but the HCS08 part does not. The only condition where the HCS08 manual specifies FACCERR while FSTAT_FCCF = 0 is (perhaps) issuing a STOP instruction, which is inconvenient to work into a program. Is this really supported on either part, or both, and are there any other caveats (such as waiting for a few cycles to ensure the command has been aborted)?

[bigmac]

Hello,

For the HCS08 parts that contain only a single flash array, there is no alternative but to disable interrupts during the erase or programming process.  For sector erase, this may occupy more than 20 ms, depending on the actual FCLK rate.

If a peripheral interrupt were to occur during the time when the flash array is inaccessible, this would mean that the interrupt vector would also be inaccessible, resulting in indeterminate program operation, with eventually a COP or ILOP reset likely occurring.

Regards,

Mac

[Potatoswatter]

I am aware of all this. My question is whether it is possible to abort the write operation, to immediately re-enable read access.

More precisely, the HCS08 manual says that a command is aborted if the MCU enters stop mode. So I could arrange for an RTC interrupt a few microseconds after a STOP instruction, handle the interrupt, and then retry the (erase) command. That sounds like a pain, and I'd like confirmation that it won't damage the device, and that there is no easier way.

Also, I'll be switching to that ColdFire v1 soon, and that manual mentions aborting the command write sequence, but not the write command itself. The list of conditions does not include anything about a stop mode. So, I need to know whether even that convoluted approach ceases to apply to that family.

Or, perhaps I will accept the increased latency. It actually isn't the end of the world.

[bigmac]

Hello,

To use entry to stop mode to abort a flash command, the code to do this would need to execute from RAM, since flash memory would be inaccessible at this point.  This method would seem feasible, whereas the direct execution of any interrupt is not feasible because of the flash based interrupt vectors.

This is the wrong forum for Coldfire issues.

Regards,

Mac