Hello,
Further to Rocco's comments, since you have set TMOD to a value of 0x00A0, the PWM period will actually be 161 cycles (not 160 cycles as you might have intended). This is because the counter does not roll over to zero until one timer clock cycle after the count reaches the TMOD value.
Another effect is that, when TCH0 register is set to 0x0000, the PWM pulse width will remain at approximately one cycle - because the PWM output toggles (high) when the timer count reaches 0x00A0, but does not return low until the OC occurs, after the counter overflows to zero. This is why special treatment of the zero duty cycle case is necessary (contrary to Rocco's comment) - simply clear the TOV0 bit within TCS0 register. This also has the consequence that the TCH0 value should be set one less than the desired duty cycle.
See what happens if you set TCH0 to the same value as TMOD - it will depend on whether "toggle on overflow" or OC actually occurs first within the device.
To smoothly change the duty cycle, without glitching the PWM output, the OC interrupt should be enabled prior to making the change, and the new value for TCH0 entered during the ISR processing. The OC interrupt can then be disabled prior to leaving the ISR, until the next change is required.
Regards,
Mac
Message Edited by bigmac on 2007-01-1503:20 PM