QG8 SCI at 230K Baud Possible ?

[Designer11]

Hello Guys,

Basically, what I'm trying  to do is to see if it is possible using either the trimmed ICS or external oscillator to obtain a 230K baud on the SCI using the QG8. I've read the AN3041 and AN3499 PDFs and looked at the two equations mentioned in the AN3041.

Eqn.1  fbus = fIRC X 512 ÷ (2 X bus divider)

Eqn.2 fbus = (fOSC÷ reference divider) X 512 ÷ (2 X bus divider)

In order to obtain a 230K baud on the QG8  the bus freq needs to be between 7.36Mhz to 7.4Mhz and the SBR12BR0 value have to be 2. Based on my calculations using the above equations the minimum  trimmed frequency is 8Mhz..

Could anyone confirm whether it's possible or not possible to obtain 230K baud on the QG8 family ?

Thanks,                                                          

[bigmac · Accepted solution]

Hello,

For a baud rate of 230400 bit/sec, you would need a bus frequency of 7.3728 MHz.  But this is not feasible using FEI mode (or FEE mode).  The reference frequency would need to be 28.8 kHz, which is outside the operating range of the DCO, and may not be trimmable.

However, it should be possible to use an external crystal or oscillator at 14.7546 MHz, using FBE mode.  But other problems may potentially arise!

The character period for this baud rate is equivalent to 16 * 2 * 10 = 320 bus cycles.  To avoid overrun errors, and loss of received data, the ISR for processing each received character would need to occupy somewhat less than 320 bus cycles, for the worst case ISR processing.  This does not allow for the processing of any other unrelated interrupt, to add further delays to the commencement of SCI receive ISR.  All other interrupts may potentially need to be disabled.

To make use of FEI mode, you would need to choose a HCS08 device having a 20 MHz maximum bus frequency.  For a baud rate divisor value of 5, a bus frequency of 18.432 MHz would be required.  This can be achieved with a reference frequency trimmed to 36.0 kHz, which is within the normal operating range.  This would also have the added benefit of increasing the number of bus cycles per character period to 16 * 5 * 10 = 800 cycles.

Whether or not overrun errors can be avoided will depend on how much processing of the received data is required, and the length of each received data burst.  Within the SCI receive ISR itself, I would suspect that there would be only sufficient time to store each new character in a buffer, with additional processing done from the main loop.

Regards,

Mac

[Designer11]

BigMac,

I have a question with the below paragraph.

"To make use of FEI mode, you would need to choose a HCS08 device having a 20 MHz maximum bus frequency.  For a baud rate divisor value of 5, a bus frequency of 18.432 MHz would be required.  This can be achieved with a reference frequency trimmed to 36.0 kHz, which is within the normal operating range. "

The equation for calculating bus frequency in ICS ( FEI mode)  is fbus = fIRC X 512 ÷ (2 X bus divider). The bus frequecy, 18.432MHz you mentioned above only works if you don't divide by (2* bus divider). So, when am i suppose to include (2x bus divider) into the equation ? 

Thanks,

[bigmac]

Hello,

For those devices capable of 20MHz bus frequency, the reference multiplying factor is increased from 512 to 1024.  For some devices, such as the 'QE32, you may select the required DCO operating range, and therefore the multiplying factor used.  Note that the 'QE8 derivative is limited to a bus maximum of 10MHz.

Regards,

Mac

[Designer11]

Hello BigMac,

Thanks for the confirmation. I'm planning on using the QGE series of uC because its bus frequency is 20Mhz which will work "nicely" with the 230K baud.