MCG external crystal for usb - s08JM60

[trav]

Hello,

I have a s08JM60 I am trying to use the usb module on, and one of the requirements is that I have an external clock so I can have a 24Mhz bus clock.  I have app note AN3560 which has code for an external 12Mhz crystal, which is what I have.  But when I run the MCG_Init() it errors out with an ILLEGAL BP.  Once I get this error I can not reconnect to the chip without a reset.  I get an unable to execute command. 

Here is the code from the app note.

void MCG_Init(){/* the MCG is set to FEI mode by default, it should be change to FBE mode at first */MCGC2 = 0x36;                     /*Select high frequency, high gain, Oscillator requested*/while(!(MCGSC & 0x02));           /*Wait for the stable of Oscillator */MCGC1 = 0x9B;                     /*External clock is selected, RDIV = 0b011 (to get 1.5MHz)*/while((MCGSC & 0x1C) != 0x08);                                  /*Check whether the external reference clock is selected */                                  /* Switch to PBE mode from FBE*/MCGC3 = 0x48;                     /*Enable PLL, VDIV = 0b1000, multiply by 32*/while ((MCGSC & 0x48) != 0x48);   /*Wait for the PLL to be locked */                                  /*Switch to PEE mode from PBE mode*/MCGC1 &= 0x3F;                     /*PLL output is selected*/while((MCGSC & 0x6C) != 0x6C);                                   /*Wait for the PLL output becoming the system clock source */return;}

The error starts at either the MCGC1 &= 0x3F;

or 

while((MCGSC & 0x6C) != 0x6C);

Could wrong value capacitors cause this?  It does kick start crystal as I can see a 12Mhz signal on the scope.

Travis

Added p/n to subject.

Message Edited by NLFSJ on 2009-04-16 09:17 AM

[pgo]

Dear trav,

What BDM are you using?  Some have a limited range of speeds over which they will operate.  You will get similar symptoms if this is the case.

If you are using OSBDM check the communication speed in the debugger after you lose communication. (under status?)

bye

For reference: My code to configure the MCG is given below.

//==========================================
// Sets up the clock for USB operation
// MGCOUT = 48MHz, BUS_CLOCK = 24MHz, (PEE mode)
//
// Assumes 12 MHz external crystal
//
// Modes: FEI (FLL engaged internal) ->
//        FBE (FLL bypassed external) ->
//        PBE (PLL bypassed external) ->
//        PEE (PLL engaged external)
//
// Refer 12.5.2.1 of MC9S08JM60 Reference
//
static void init_clock(void)
{
   // Out of reset MCG is in FEI mode
  
   // 1. Switch from FEI (FLL engaged internal) to FBE (FLL bypassed external)
  
   // 1 a) Set up crystal
   MCGC2 =                       // BDIV = 0, divide by 1
            MCGC2_HGO_MASK       // oscillator in high gain mode
          | MCGC2_EREFS_MASK     // because crystal is being used
          | MCGC2_RANGE_MASK     // 12 MHz is in high freq range
          | MCGC2_ERCLKEN_MASK;  // activate external reference clock
 
   // 1 b) Wait for crystal to start up       
   while (MCGSC_OSCINIT == 0) {
   }
 
   // 1 c) Select clock mode
   MCGC1 =   (2<<6)   // CLKS = 10 -> External reference clock
           | (3<<3);  // RDIV = 3  -> 12MHz/8=1.5 MHz
 
   // 1 d) Wait for mode change
   while (MCGSC_IREFST != 0) {
   }
  
   // 1 e) Wait for MCGOUT indicating that the external reference to be fed to MCGOUT
   while (MCGSC_CLKST != 2) {
   }
  
   // 2. Switch FBE (FLL bypassed external) to PBE (PLL Bypassed External) mode
  
   // 2 b) Set RDIV for correct range
   // 2 c) Enable the PLL & set VDIV value
   MCGC3 = MCGC3_PLLS_MASK
         | (8<<0);        // VDIV=6 -> multiply by 32 -> 1.5MHz * 32 = 48MHz */
  
   // 2 e) Wait until PLLS clock source changes to the PLL
   while(MCGSC_PLLST != 1) {
   }

   // 2 f)  Wait for PLL to acquired lock
   while(MCGSC_LOCK != 1) {
   }
  
   // 3. PBE mode transitions into PEE mode:

   // 3 a) Set RDIV for correct range and select PLL.FLL clock
   MCGC1 =   (0<<6)       // CLKS = 0 -> PLL or FLL output clock
           | (3<<3);      // RDIV = 3 -> 12MHz/8=1.5 MHz (req. 1 < f < 2)

   // 3 c)  Wait for clock stable
   while(MCGSC_CLKST!=3) {
   }

   
  /* Now MCGOUT=48MHz, BUS_CLOCK=24MHz */ 
}

Message Edited by pgo on 2009-04-18 05:29 PM

Message Edited by pgo on 2009-04-18 05:29 PM

[trav]

pgo,

I'm using a WTUSBDML which is a witztronic bdm.  After reading the specs for it again on thier web page, it does say a limit bus speed of 20Mhz. 

The OSBDM status did say 48Mhz, but the BDM status reg right about it reads 0x64(secured?).

My question now is what bdm's support speeds that fast.

Travis

[pgo · Accepted solution]

Dear trav,

If you are using WTUSBDM there is an option to use a different clock source for the BDM interface.

On the dialogue that pop ups when connecting try selecting "Force BDM clock source"  and try the two alternatives.  If you're lucky one should work ok.

bye

[trav]

Yes this worked!

I had to install the opensourcebdm.dll file, because I was not seeing the menu you were talking about.