MC9S08QD4 bus speed, is it really 8Mhz??

[sauliuz]

    Hello,

Just received new MC9S08QD4 micros. It says that it has 16MHz core and should have 8MHz bus speed. Trying to test it. Just a very simple program on CodeWarrior below. Timer that overflows after single tick (TMOD=1). But I see 104.2kHz on PTA0 with scope. What do I do wrong? (no external oscilator, INTERNAL)

#include <hidef.h> /* for EnableInterrupts macro */
#include "derivative.h" /* include peripheral declarations */

interrupt 7 void TimerOverflowInterrupt() { //TIMER OVERFLOW INT
  TPMSC_TOF = 0;
  PTAD_PTAD0 = ~PTAD_PTAD0;
}

void InitializeTX(void) {
  TPMSC_TOIE = 0;  //Timer TPM1CH0 disable 0
  PTADD_PTADD0 = 1;
  TPMSC_CLKSB = 0;
  TPMSC_CLKSA = 1; // 01 bus clock
  TPMSC_PS2 = 0;
  TPMSC_PS1 = 0;
  TPMSC_PS0 = 0;  // clock not devided
  TPMMODH = 0;
  TPMMODL = 1;  // free run

  TPMC0SC_CH0IE = 0;  // 0 - channel interrupt disable
  TPMC0SC_MS0B = 0;
  TPMC0SC_MS0A = 1;
  TPMC0SC_ELS0B = 0;
  TPMC0SC_ELS0A = 0;

  TPMSC_TOIE = 1;  //Timer TPM1CH0 enable
}

void main(void)
{

SOPT1_COPE = 0; // 0 - disable watchdog, 1 - default after reset

 EnableInterrupts;
 
 InitializeTX(); 

 for(; {
  } /* loop forever */
}

[bigmac]

Hello,

The device would be operating as anticipated.  Since you are processing the TPM overflow interrupt, this will require many cycles to complete.  So the ISR is being entered only once in every umpteenth overflow.

If you wish to check the bus frequency, I would suggest that you setup the TPM for PWM mode, with about 50 percent ON period.  The output frequency should then correspond with the TPM overflow period, which will need to be two cycles, or more.

Regards,

Mac

[sauliuz]

Thank you for the remark.  Then we get even simpler code. Now I see 2MHz on the scope. Is it possible that to jump from overflow to 0 timer needs additional 7 clock cycles? Were are 8 MHz?



#include <hidef.h> /* for EnableInterrupts macro */
#include "derivative.h" /* include peripheral declarations */

void InitializeTX(void) {
  TPMSC_TOIE = 0;  //Timer TPM1CH0 disable 0
  PTADD_PTADD0 = 1;
  TPMSC_CLKSB = 0;
  TPMSC_CLKSA = 1; // 01 bus clock
  TPMSC_PS2 = 0;
  TPMSC_PS1 = 0;
  TPMSC_PS0 = 0;  // clock not devided
  TPMMODH = 0;
  TPMMODL = 1;
  TPMC0SC_CH0IE = 0;  // 0 - channel interrupt disable
  TPMC0SC_MS0B = 0;
  TPMC0SC_MS0A = 1;
  TPMC0SC_ELS0B = 0;  // now working in output compare toggle mode
  TPMC0SC_ELS0A = 1;
}

void main(void)
{

 SOPT1_COPE = 0; // 0 - disable watchdog, 1 - default after reset

 EnableInterrupts;
 
 InitializeTX();

 for(; {
  } /* loop forever */
}

[thisobj]

Hello sauliuz,
The default out-of-reset value for BDIV bits in ICSC2 is "01", which will cause the clock source to be divided by 2 and will result in a default bus clock of 4Mhz.  You should write zeros into the BDIV bits to avoid the additional divide by 2.  This should give a bus clock of 8Mhz.

Regards,

Frank
 

[sauliuz]

thank you thisobj. missed it while reading.
but there is one more thing that is not quite clear to me.

If I add command ICSC2_BDIV = 0; to my last program in the start procedure I get 4MHz signal. Hence Timer counting way should be like this:

0-(clock cycle)->1-(overflow detected, clock cycle)->0-(clock cycle)->1

But I thought that it emediatly goes back to 0 when recheaes TPMMOD, like this:

0-(clock cycle)->1-(overflow detected)->0-(clock cycle)->1

And then I should see 8 MHz on scope.

How does it work?

[thisobj]

Hi Sauliuz,

Your first analysis is closer to being correct:

          0-(clock cycle)->1-(overflow detected, clock cycle)->0-(clock cycle)->1

But it probably isn't correct to refer to an "overflow" in OC mode, since the events occur when the number of input clock pulses match the register value .  More likely, the sequence for output compare mode with toggle selected should be:

          0-(clock cycle)->1-(register match, reload value, clock cycle)->0-(register match, reload  
          value,  clock cycle)->1

Regards,

Frank

[sauliuz]

Thank you all for answers, now it is clear.

[bigmac]

Hello,

Since you have set up the TPM channel to toggle on output compare (I assume that the TPM channel register remains at the default value of zero), and with a TPMMOD value of 1,  the output should toggle every two bus cycles.  Therefore to complete a full cycle at the output should require a total of four bus cycles.

The following is a brief excerpt from the data sheet -

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock . . .

Regards,

Mac

Message Edited by bigmac on 2007-10-04 12:02 AM

[Alban]

Hello,

The core has a maximum speed of 16MHz.

You need to configure the ICS module with the FLL/PLL to achieve the frequency you desire from the internal clock of 32kHz.

I do not have code.

Alban.