Hello,
Thank you for your help. But now I have the new problems, when I use interrupt to receive a data, the problem can't enter into the ISR.
I have enabled the SCI0_RIE=1; Following is the details:
Receiver Interrupt Enable for RDRF
0 Hardware interrupts from RDRF disabled; use polling.
1 Hardware interrupt requested when RDRF flag is 1.
And after send the data the RDRF flag has changed to 1, but the ISR did not run. The ISR code is as following:
void main(void) {
DisableInterrupts; /* enable interrupts */
MCU_init(); /* call Device Initialization */
Init_SCI0(); /* call Device Initialization */
EnableInterrupts;
while(!(SCI0_S1&0X80));
SCI0_D=0b00000011; //send the data
if (rx==0x03)
flag=1;
else
flag=0;
}
__interrupt void isrVsci0rx(void)
{
dummy=SCI0_S1; // 清除s1标志位第一步
rx=SCI0_D;
//EnableInterrupts;
}
__interrupt void isrVsci0rx(void)
{
dummy=SCI0_S1; // 清除s1标志位第一步
rx=SCI0_D;
//EnableInterrupts;
}
static void (* near const _vect[])(void) @0xFFB0 = { /* Interrupt vector table */
/*lint -restore Enable MISRA rule (1.1) checking. */
UNASSIGNED_ISR, /* Int.no. 39 Vnvm (at FFB0) Unassigned */
UNASSIGNED_ISR, /* Int.no. 38 VReserved38 (at FFB2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 37 Vkbi0 (at FFB4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 36 VReserved36 (at FFB6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 35 Vrtc (at FFB8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 34 VReserved34 (at FFBA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 33 VReserved33 (at FFBC) Unassigned */
UNASSIGNED_ISR, /* Int.no. 32 VReserved32 (at FFBE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 31 VReserved31 (at FFC0) Unassigned */
UNASSIGNED_ISR, /* Int.no. 30 VReserved30 (at FFC2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 29 VReserved29 (at FFC4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 28 VReserved28 (at FFC6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 27 VReserved27 (at FFC8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 26 VReserved26 (at FFCA) Unassigned */
isrVsci0tx, /* Int.no. 25 Vsci0tx (at FFCC) Used */
isrVsci0rx, /* Int.no. 24 Vsci0rx (at FFCE) Used */
isrVsci0err, /* Int.no. 23 Vsci0err (at FFD0) Used */
UNASSIGNED_ISR, /* Int.no. 22 Vadc (at FFD2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 21 Vacmp (at FFD4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 20 VReserved20 (at FFD6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 19 VReserved19 (at FFD8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 18 Vftm0ovf (at FFDA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 17 Vftm0ch1 (at FFDC) Unassigned */
UNASSIGNED_ISR, /* Int.no. 16 Vftm0ch0 (at FFDE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 15 Vftm1ovf (at FFE0) Unassigned */
UNASSIGNED_ISR, /* Int.no. 14 Vftm1ch1 (at FFE2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 13 Vftm1ch0 (at FFE4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 12 VReserved12 (at FFE6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 11 VReserved11 (at FFE8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 10 VReserved10 (at FFEA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 9 VReserved9 (at FFEC) Unassigned */
UNASSIGNED_ISR, /* Int.no. 8 VReserved8 (at FFEE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 7 VReserved7 (at FFF0) Unassigned */
UNASSIGNED_ISR, /* Int.no. 6 VReserved6 (at FFF2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 5 VReserved5 (at FFF4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 4 Vclk (at FFF6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 3 Vlvw (at FFF8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 2 Virq_wdog (at FFFA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 1 Vswi (at FFFC) Unassigned */
_Startup /* Int.no. 0 Vreset (at FFFE) Reset vector */
};
在 2013-05-22 03:58:22,bigmac <admin@community.freescale.com> 写道:
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MC9S08PA4 SCI debugging problems
created by bigmac in 8-bit Microcontrollers - View the full discussion
Hello,
Since you have enabled transmit interrupts, you will need an interrupt handler. If you do not have one, the MCU will most likely hang, eventually resulting in a COP timeout (unless the COP has been disabled). Perhaps you do not need to use transmit interrupts.
void SCI_sendchar( byte c)
{
while ((SCI0_S1 & 0x80) == 0); // Wait for TDRE flag set
SCI0_D = c;
}
Regards,
Mac
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