Hello,
The SPI module, when configured for 8 data bits and no parity, will generate a start bit followed by the data bits and then a stop bit. My understanding is that, enabling parity within the SPI module will cause an additional parity bit to be inserted between the last data bit and the stop bit - not what you require.
The only solution that I can see is to leave the setting for 8-data bits, no parity. You would then need to calculate the odd parity bit for each data byte, and change the MSB of the byte to suit the parity. Then send the modified byte to the SCI.
Perhaps something like the following untested code would work:
// Returns 7 data bits + odd paritybyte odd_parity( byte val){ byte i, temp; byte parity = 0x80; // Initialise for odd parity temp = val & 0x7F; for (i = 0; i < 7; i++) { val <<= 1; parity ^= val; } return ((parity & 0x80) | temp);}
SCI1D = odd_parity( value);
For received data, you may wish to simply ignore the parity bit, so zero the MSB of the received byte.
Regards,
Mac