If I had enough hair to spare I'd be pulling it out over this. This flash programming routine *USED* to work, until I went through all my code and took out the use of the COP timer. I must have done something but I'll be darned if I can find it. Someone, please have a look and make a suggestion. I'd appreciate it. It was derived from an app note and section 4.4.4 of the data sheet.
The facts:
I get an access error (FACCERR set) when I attempt to program.
The FCDIV register was written with $98 just after reset (BusClk=14.68MHz, FlashClk=180KHz).
The NVPROT register is $98 (FPOPEN set & $F000-$FFFF protected).
The NVOPT is $FE although I didn't do it (debugger?). Sec1
ec0 = 10 = unsecured.
The strange thing is, FACCERR is becoming set as soon as the instruction to clear it is executed. If you'll notice the "###" within the comments, that's where I'm grabbing and saving the FSTAT register. The 3 samples of FSTAT (at $FB, $FC, $FD) are $C0, $D0, $D0. So, you see that FACCERR is getting set when it is supposed to be getting cleared.
Here's the code (that runs from RAM):
The facts:
I get an access error (FACCERR set) when I attempt to program.
The FCDIV register was written with $98 just after reset (BusClk=14.68MHz, FlashClk=180KHz).
The NVPROT register is $98 (FPOPEN set & $F000-$FFFF protected).
The NVOPT is $FE although I didn't do it (debugger?). Sec1
ec0 = 10 = unsecured.The strange thing is, FACCERR is becoming set as soon as the instruction to clear it is executed. If you'll notice the "###" within the comments, that's where I'm grabbing and saving the FSTAT register. The 3 samples of FSTAT (at $FB, $FC, $FD) are $C0, $D0, $D0. So, you see that FACCERR is getting set when it is supposed to be getting cleared.
Here's the code (that runs from RAM):
;********************************************************************* ; When FLPROG is called, stack is a mess. It looks like: ; 1:2,sp Return addr (to Progflash). ; 3:FLprogSize+2,sp This subroutine. ; FLprogSize+3:FLprogSize+4,sp Flash address to be prog. ; FLprogSize+5,sp Byte Count (0=256). ; FLprogSize+6:FLprogSize+7,sp Return addr. ; FLprogSize+8:FLprogSize+9,sp Source address of prog data. FLPROG LDX FSTAT ;### TEST STX $FB ;### TEST. Saved FSTAT is $C0 sta FSTAT ;abort any command and clear errors (A = $30) FLPROG2 LDA FSTAT BPL FLPROG2 ;WAIT FOR FCBEF SET (READY 4 CMND). STA $FC ;### TEST. Saved FSTAT is $D0, FACCERR set! LDHX LOW(FLprogSize+8),SP ;GET SOURCE ADDR. ($0198) LDA 0,X ;GET DATA AT SOURCE. AIX #1 ;BUMP SOURCE ADDR. STHX LOW(FLprogSize+8),SP ldhx LOW(FLprogSize+3),sp ;get flash address from stack ($8200) sta 0,x ;write to flash; latch addr and data AIX #1 ;BUMP FLASH ADDR. STHX LOW(FLprogSize+3),sp lda #$25 ;get flash command, Burst Program. sta FCMD ;write the flash command lda #$80 sta FSTAT ;[pwpp] register command nop ;[p] want min 4~ from w cycle to r NOP LDA FSTAT STA $FD ;### TEST. Saved FSTAT is $D0 (FACCERR still set) BIT #%00110000 BNE FLprogEnd ;error if FPVIOL or FACCERR bit set. DBNZ LOW(FLprogSize+5),sp,FLPROG2 ;do for COUNT bytes. CkFPDone lda FSTAT ;[prpp] so FCCF is valid lsla ;FCCF now in MSB bpl CkFPDone ;Loop until prog complete. FLprogEnd rts ;back into ProgFlash in flash FLprogSize equ (*-FLPROG)
