Message Edited by Alban on 2006-12-11 09:25 PM
*********** Set-up ICG to clock the bus at 19.9954 MHz ********************** LDA NVICGTRIM ;get calibration value from FLASH STA ICGTRM ;set oscillator trim value MOV #(mMFD2|mMFD1|mMFD0),ICGC2 ;sets MFD divider MOV #mCLKS0,ICGC1 ;243 kHz -> 19.9954 MHz bus rate BRCLR LOCK,ICGS1,* ;loop until FLL locks