Keep /SS low during a whole SPI transmission

[Limestone]

Hi!

I am trying to interface a common AT26DF0B1A spi data flash from my MC9S08QE128

I am using the SynchroMaster bean in PE 3.06 on CW 6.2

When i use the code below, i cant read anything back from the  dataflash. The attatched image withspiss.png shows that /ss moves to high after each transmission.

If i however control the /ss myself with a bitIO bean and uncomment the lines marked with NOTE 1 and 2 i do get data back. See  with manualSS.png.

Is there a way to keep /SS low during all the data in the TX buffer with the automatic /SS in syncromaster so that i dont have to manage the /SS pin manually?

 
long get_flash_id() {
    long val;
    char buff;
    word c;
    unsigned char id[] = {0x9F,0,0,0,0 } ;
    // ExtMem_CS_ClrVal();  // NOTE 1

    ExtMem_ClearRxBuf();

    ExtMem_SendBlock(id,5,&c);

    val = ExtMem_GetCharsInRxBuf();
    while(val < 5) {
        val = ExtMem_GetCharsInRxBuf(); 
    }

    ExtMem_RecvChar(&buff);

    val = (long) (((long)buff) << 24);
   
    ExtMem_RecvChar(&buff);

    val = val | (long) (((long)buff) << 16);
   
    ExtMem_RecvChar(&buff); 

    val = val | (long) (((long)buff) << 8);
   
    ExtMem_RecvChar(&buff);    

    val = val | buff;
   
    // ExtMem_CS_SetVal();  // NOTE 2
    return  val;
}

Best Regards

Martin

withSPISS.png

withmanualSS.png

Message Edited by t.dowe on 2009-12-02 11:16 AM

[ProcessorExpert · Accepted solution]

Hello,
 
SPI periphery does not support such functionality. SPI device handles SS pin with every sent byte (word) according to CPOL, CPHA bits (Shift clock iddle polarity, Clock edge properties) setting.
 
I think your step to use BitIO bean to toggle SS pin was correct.
 
For more details about setting CPOL and CPHA bits (Shift clock iddle polarity, Clock edge properties) please see help from pop-up menu of Synchromaster bean or reference manual of QE128.
 
best regards
Vojtech Filip
Processor Expert Support Team