IO Port speed does not match BUSCLK frequency

[RastislavMatula]

Hi All,

Just a quick question, maybe this is another basic thing, but it seems I missing something. I am trying to drive IO pin (among other things ) and is vital for the project to drive it as fast as possible. I am using S08JM60 mcu, CW 10.1 with PE (-Ot), 2MHz external crystal (set so the "Internal Bus Clock" = 24MHz, "PLL output cock freq." = 48MHz ). Looking in the assembly code i could see:

34

SCLK_SetVal();

1bda:   1E06 BSET 7,0x06

36

SCLK_ClrVal();

1bdc:   1F06 BCLR 7,0x06

I am assuming that each of this instructions should take only one clock cycle (BUSCLK=24MHz), so the pulse length   __|'''''''''|__  should be ~41,6ns. But obviously I can see something different on oscilloscope, where the pulse length is ~208ns (4.8MHz). It seems, that everything is running slower than I think the real possibilities are. Could somebody enlighten me into this?  What about core frequency, shouldn't be execution of instruction even faster (48MHz) if i am not trying to access GPIO? Is it possible to twiddle with IO faster than 200ns?

Thanks for your time,

Rasto.

[kef · Accepted solution]

See 7.5 HCS08 Instruction Set Summary in JM60 datasheet. BSET and BCLR each take 5 bus clock cycles. Thta's why you see pulse width of 5 bus clock cycles.

STA and STX instructions with DIR address mode take 3 cycles. You can preload A and X registers with bit masks to set and clear specific pin, then usa STA and STX to toggle pin little faster.

[RastislavMatula]

Thank you very much for quick reply.

Well, that's quite new information for me, when I look to instruction set summary :smileyhappy:. I was under impression, that S08 is faster than atmega, since it could run at much higher frequency. I guess I always jumped over that "big ugly table" never caring about its content. Anyway I will tray to deal with it somehow, but it is good to know what is the root cause.

Thanks a lot,

Rasto.