ICS protection against loss of lock an loss of clock

[matri]

Hello,

I'm currently using a QE8 microcontroller in my application. The ICS module is designed for lower power operation and has no features that allow monitoring of loss of lock or loss of clock. I read  AN3499, on paragraph 2.1.7, in the event of loss of lock, the ICS attempts to regain FLL on its own. I have doubt on this sentence, it means that the microcontroller change it mode of operation and come in default mode, FEI, if a loss of lock occur?

The ICS module contains an indipendent clock source for the COP watchdog timer that can rest the MCU if the CPU and bus clocks are corrupted. I suppose to enable the COP watchdog and use for it the indipendent clock source (1KHz clock), if a loss of clock occur, betwen this event and the COP reset the MCU, the bus frequency falls to 0Hz?

Thanks in advance.

Marilena

[bigmac]

Hello Marilena,

Do you have an experience where the FLL did not attempt to regain lock?

The ICS should continue in the currently selected mode, unless there is a reset.  Using the internal reference, any loss of lock will be temporary, maybe due to a step in Vdd voltage.  I can't think of any other causes.

Using an external reference, loss of this reference, for any reason, would cause loss of lock and loss of clock.  However, a reset would need to occur to revert to FEI mode.  Under these circumstances, using the independent COP clock source would eventually result in a reset, as you suppose.

Regards,

Mac

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