I am wondering if it's possible to setup the TPM to simpl...

[awmark]

I am wondering if it's possible to setup the TPM to simply use the timer function without any pin control for multiple channels.  So if I set TPM1C0SC to 0x40, I think I am enabling the timer channel 0 interrupt, but disabling the pin control.  But it appears the interrupt never occurs.  I can only get the general overflow function to work:

  TPM1MOD   = 0x3fff; // Modulo value
  TPM1C0V   = 0;         // Channel interrupt will happen when counter matches
  TPM1C0SC  = 0x40; // Enable channel interrupt, but don't affect I/O
  TPM1SC    = 0x17;    // Overflow interrupt disabled, using bus rate clock, prescaler = 128

Is that just impossible?

Thanks,

Mark

[kef]

Mark,

do you want timer Output Compare without pin set/clear/toggle control? If so then try setting MSnB:MSnA to 01 (output compare), keeping ELSnB:ELSnA ==00. On QE128 this seems to work. I wonder why such mode is not listed in mode selection table. Definitely such mode is useful and is needed.

[awmark]

Kef,

That does work!  Thanks.  Of course, I too wonder why it's not listed.  But now the interrupt hits.

Mark

[awmark]

Now I can generate multiple interrupts off a single timer, which was really my objective.

Is it efficient? Maybe. Is it the 'right' way?  I suppose it depends on what I'm trying to accomplish.  For simple software trigger mechanisms (implied, since no pin control), it may be fine.

[JimDon]

For what it's worth, the manual clearly states this:

"Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin"

[allawtterb]

---

awmark wrote:

  TPM1SC    = 0x17;    // Overflow interrupt disabled, using bus rate clock, prescaler = 128

This is selecting the fixed system clock, you want to set it to 0x0F to use the bus clock for the counter input.  Are you sure that you are clearing the flags properly in your ISR?  Have you checked to see if CH0F in TPM1C0SC is set or cleared? 

[JimDon]

Yes, it is possible to use the timer interrupt with out pin control.
You need to set the compare register in the init code and in the interrupt handle with the value of the counter register plus how many count in the future in want the interrupt to happen.


TPM1C0V = TMP1CNT + mydelay;


I don't have the spec in front of me, so you may have missed something else, but it is possible and you do need to keep updating the compare register in the handler as I have shown.

[awmark]

Thanks, Jim.

I don't know what else I could be missing either, as the channel 0 interrupt never gets entered.

I did as you suggested and set the TPM1C0V value to the count + my delay.  No difference.

I see the interrupt declared in CodeWarrior's vector table and the ISR is defined.  I have other ISRs, like the overflow ISR that work just fine.  It also works when I set the mode (in TPM1C0SC) to some non-zero value.

But I agree that maybe some other seemingly unrelated setting may be causing the problem.

Mark

[JimDon]

"A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous CHnF."

In the init:
TMPxCnSC &=  0x7F; (this will read it and clear it)

and something like this in the handler:

if( TMPxCnSC & 0x80 )  // you don't really need the if.
  TMPxCnSC &=  0x7F;

But use the proper defines...

[awmark]

Jim,

Except for the initial value, that's what I was doing.  When I cleared the initial flag, it made no difference.

The interrupt still never fires.

Mark

[peg]

Hello and welcome to the fora Mark,

Firstly please include the device in question in the subject.
Presuming S08 family here.
If you look at the TPM block diagramme you will see that the pin output and channel interrupt are optional extras based on the state of CHxF. So yes the timer still works with no pin output OR interrupt or any other combination.
This makes the obvious troubleshooting startegy to look at CHxF as Brett has suggested.

Possible stategy:

Slow your timer clock down as slow as possible.
disable the timer interrupt.
write a simple polling routine that resets the flag and toggles an output (Preferably connected to an LED)
If that works then you can worry about getting the interrupt working.

[awmark]

Thanks.

It would appear that the overflow interrupt works but the channel interrupt appears to be disabled when no activity is selected for the output pin.  I think they should put that in BOLD letters somewhere.  It's probably obvious to the designer...

Mark

[peg]

Hello Mark,

The timer overflow and its interrupt are totally independant from the channels, they just all work with a common counter register. With all modes of the channel the overflow operation is unaffected.

Which manual are you referring to?
The ones I have looked at make it abundantly clear (especially in the table that shows all the cobinations for CPWMS, MSnX and ELSnX) how the various combinations of modes and pin control modes all work.

As stated before the block diagram also shows this.

[kef]

Right, the problem is we didn't mention part numbers. QE128 reference manual rev2 doesn't list MS=01, ELS=00 mode in Table 16-6.  But QD4 datasheet rev3, lists that mode in Table 11-5.

[JimDon]

In a way it does, by saying X XX:00 but that is not clear.

However the QE128 manual says (p296 Table 16-5):

Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin.

Added p/n to subject.

Message Edited by NLFSJ on 2008-06-30 02:32 PM

[allawtterb]

The XX:00 in Table 16-6 (I am looking at the DZ datasheet) is the problem, it implies that when ELSnB:ELSnA is 00 that MSnB and MSnA have no affect on how the channel behaves.

[JimDon]

Well, I suppose you could decide it means that, but the text entry in the table does not say that. It says that the pins are disconnected regardless of any other setting. It says nothing regarding other functions of the modules.

I am just attempting to help others understand what the RM is telling you. You have to carefully read what it says and assume nothing more. Not that I have not spent hours myself, reading and re-reading a modules specification to overcome assumptions I have perhaps made but that were not actually stated.

[peg]

Perhaps our esteemed manual authors should take a look at the table in the GT16A manual and then change the ones that aren't so clear to something like it.

[bigmac]

Table 16.5 in the QG8 datasheet is also perfectly explicit on this issue.

Regards,

Mac

[bigmac]

Hello Mark,

I notice that you have set the TPM modulo value to 0x3FFF.  If the channel register value happens to exceed this value, no interrupt will occur.  For the purpose of your tests, I would suggest to leave the TPM in default free running mode (TPM1MOD = 0), so that you should get a TPM compare interrupt once every TPM overflow cycle, whatever the channel register value.

Note that, with an overflow count of less than the default of 0xFFFF, the calculation of the time for the next compare event will also need to take into account the modulo value used, requiring a more complex calculation.

Regards,

Mac