Thanks for your response,
I want to know some more details about calculating BUSCLK(24MHZ) using 4MHZ external crystal.
*When i go through the datasheet for setting RDIV register (i.e Page no 140 If the FLL is selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected,the resulting frequency must be in the range 1 MHz to 2 MHz).
*Operational Modes i'm using FEE(FLL Engaged External) FLL as Clock Source Select.
For generate the 24MHZ BUSCLK ,FLL Clock Source can not be use as my understanding, Need to Use PLL Clock Source. How i should configure the MCG Control Register to get the MCGOUT = 48Mhz so BUSCLK=24Mhz .
MCG Register's Initialization
/* MCGC2: BDIV=00,RANGE=1,HGO=0,LP=1,EREFS=1,ERCLKEN=1,EREFSTEN=1 */
MCGC2 = 0x2F;
/* MCGC1: CLKS=00,RDIV=001,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCGC1 = 0x08;
/* MCGC3: LOLIE=0,PLLS=1,CME=0,VDIV=1000 */
MCGC3 = 0x46;
while(!MCGSC_OSCINIT) /* Wait until external reference is stable */
while(MCGSC_IREFST) /* Wait until external reference is selected */
while(!MCGSC_LOCK) /* Wait until FLL is locked */
while((MCGSC & 0x0C) != 0x0C) /* Wait until PLL clock is selected as a bus clock reference */
Please help me to if any wrong values settings.
Thanks In Advance.