How to generate a 2.4576MHz Bus clock using Internal Clock reference from ICS?

[Johannie]

Hi,

I'm using HCS08 series M9S08SG32 Controller, I wanted work on slow speed mode. I've gone through document for Internal Clock Source but I really no cleared about, how we can generate a 2.4576MHz clock from internal clock reference of ICS module.And most important thing is I want to use Internal clock source only (Not external crystal oscillator)  Can any one suggest me how can I do the same.

Thanks in advance...

J.

[bigmac]

Hello Johannie, and welcome to the forum.

Firstly, what frequency accuracy do you require?  The initial trimming accuracy is 0.1 percent, but the bus frequency will be subject to a possible termperature drift of +/-1.5 percent for normal temperature range, and +/-3 percent for extended temperature range device.  Will this be sufficiently accurate for your project?

The internal reference may be trimmed within the range 31.25 kHz to 39.06 kHz.  The FLL will then generate a DCO output frequency within the range 32 MHz to 40 MHz.  This would then be reduced by a BDIV factor of 8, for ICSOUT frequency of 4MHz to 5MHz.  There is a further divide by 2 factor, to give a bus frequency range of 2.0 MHz to 2.5 MHz.  The frequency that you require is near the upper end of this range.

Now working backwards, to achieve a bus frequency in the vicinity of 2.4576 MHz would require an internal reference frequency of 38.4 kHz.  However, since the trim value determined by the factory is based on 31.25 kHz internal reference frequency, a special calibration procedure would be necessary to deternine the correct trim value.

If your reason for choosing a bus frequency of 2.4576 MHz is to facilitate standard baud rates for the SCI module, provided you do not require greater than 9600 bits per second, a trimmed bus frequency of 2.0 MHz could alternatively used, in conjunction with a baud rate divisor setting of 13, or a multiple.  This would mean that the factory trim value could be utilized, or a standard calibration procedure by the BDM programming device.

Regards,

Mac

[Johannie]

Hello Johannie, and welcome to the forum.

Thank  you  Mac for reply,

Firstly, what frequency accuracy do you require?  The initial trimming accuracy is 0.1 percent, but the bus frequency will be subject to a possible termperature drift of +/-1.5 percent for normal temperature range, and +/-3 percent for extended temperature range device.  Will this be sufficiently accurate for your project?

Yes, my project is Down Hole Tool so I'm going to use it for higher temperature range only. But the controller will communicate in normal temperature range only. In communication mode temperature range is not a big issue for now.

The internal reference may be trimmed within the range 31.25 kHz to 39.06 kHz.  The FLL will then generate a DCO output frequency within the range 32 MHz to 40 MHz.  This would then be reduced by a BDIV factor of 8, for ICSOUT frequency of 4MHz to 5MHz.  There is a further divide by 2 factor, to give a bus frequency range of 2.0 MHz to 2.5 MHz.  The frequency that you require is near the upper end of this range.

Now working backwards, to achieve a bus frequency in the vicinity of 2.4576 MHz would require an internal reference frequency of 38.4 kHz.  However, since the trim value determined by the factory is based on 31.25 kHz internal reference frequency, a special calibration procedure would be necessary to deternine the correct trim value.

If your reason for choosing a bus frequency of 2.4576 MHz is to facilitate standard baud rates for the SCI module, provided you do not require greater than 9600 bits per second, a trimmed bus frequency of 2.0 MHz could alternatively used, in conjunction with a baud rate divisor setting of 13, or a multiple.  This would mean that the factory trim value could be utilized, or a standard calibration procedure by the BDM programming device.

Mac my aim for choosing a bus frequency of 2.4576 MHz is to facilitate standard baud rates for SCI module only. And I really not required greater than 9600 baud rate.

Thanks for giving the work around for the problem, I will try this and will update if able to do it successfully.

But I really wanted to know about the ICS, is there any document available which will give me information as you explained, FLL will generate the DCO out frequency, then we can divide by BDIV and so on...cause I not found any information about the DCO or how it works for the Freescale controllers through out the controller datasheet... So I can do it my self..

Regards,

Mac

[bigmac]

Hello Johannie,

The information that I used is present in the datasheet, but you need to look in a number of places.  Obviously Chapter 11: Internal Clock Source (ICS) is important.  Additionally, fig. 1.2 shows the system clock distribution, and Appendix A.9 provides information on trim ranges, etc.

However, you might also examine Application Notes AN3041 and AN3499 for additional information.

Regards,

Mac