Doesn't release reset

[digisnapmark]

Hiya's

9S08MP16.  Configured reset pin to be a reset input. Using internal clock.

I've got most of the code working fine, was going through some details before spinning the layout.

Noticed that when the Reset line is externally pulled low momentarily, the chip does indeed enter reset, but never leaves Reset state, until power cycle. The chip is holding the reset line low (even with an additional pull-up), and is dead to the world.

Any ideas?

Tanks,  Mark

[bigmac]

Hello Mark, and welcome to the forum.

The only reason for a held reset state that comes to mind is that, should there be a sufficient sag of the Vdd level, it could be possible for the LVD module to not release the reset state.  But this would require a very significant drop in voltage level after the external reset state is applied.

I am not aware that the reset pin for this device ever becomes an output during the reset procedure, and the POR default state is as an external reset pin.  Therefore, if the pin state remains low, I would have suspicions about the operation of the external reset circuitry.

You might termporarily place a series diode, with its anode connected to the reset pin, and with pullup resistors on each side of the diode.  You should then be able to determine whether the held low state is caused by the MCU, or the exteral reset circuit.  If caused by the MCU, the voltage at the diode cathode will remain a high state.

Regards,

Mac

[digisnapmark]

Thanks for the response!

Vdd is rock solid... no sag during reset.

The MP16 reset pin is an open drain with pullup, and the chip clamp the pin for 34 clock cycles after reset is initiated... per the data sheet.

Good call on the external reset circuit check. I'm an old analog guy, so I played a trick... instead of using an external switch to ground to trigger reset, I used a switched resistor to ground, of the same relative value as the pull-up (10K in this case).  As the resistor is switched in, the voltage on the RESET pin starts to RC ramp down to Vdd/2. About 1 uS into the ramp, as it starts to approach Vdd/2, the chip resets, and clamps the voltage hard to ground. Makes for a pretty pic on the o'scope.

Tis pretty definitive, the external signal is triggering the reset, but the chip does indeed take over, and never releases the RESET line, until a power cycle (POR). It's like the clock is inhibited when reset via RESET pin.

Reading the SRS always yields $82 (POR), which makes sense, as this was indeed the last reset before the chip started running again.

Time to put in a new chip.. make sure it's not h/w.

[digisnapmark]

Same behaviour with new chip.

[digisnapmark]

I also tested this using an illegal address reset, and it does the same thing.  The RESET line goes low, and stays low until power cycling the chip.

[digisnapmark]

OMG... finally found it.  Freescale support couldn't figure it out, but at least supplied me with example startup code that didn't exhibit the same problem, so I eventually found it.

Setting Bit 5 (LVDV) on SPMSC2 prevents the resets from working properly on my board (3.15V supply)... POR is required to complete the reset.

Whew!

[bigmac]

Hello,

I do not recall that this specific issue has ever been raised previously in this forum - an am a little surprised that it has not.

When a POR occurs, LVD reset is enabled and the LVD threshold defaults to low range.  The LVD reset will be released once Vdd exceeds about 2.6 volts.  Presumably your code was then setting the LVD threshold to high range.  This would mean that any Vdd level below 4.0 volts would cause LVD reset which would continue until a POR occurred (when the LVD threshold again changes to low range).

I might have intuitively expected that the reset state would have occurred immediately after changing the LVD range.  But from your observations, this is apparently not so.  Under this condition, the LVD reset would seem to need a reset from another source to trigger its correct operation.  This operational quirk would appear to be undocumented, and may also apply to many other MC9S08 types.

Regards,

Mac

[Lundin]

I'm just guessing but here is my belief of how it would work:

I believe the LVD kicks in immediately when you write to that bit. Then it keeps the reset line low as long as the voltage is considered bad. Otherwise it wouldn't be much of a LVD, the alternative would be to attempt to restart the MCU with improper supply voltage, which is of course a big no-no. If the MCU remains in reset, the LVD registers aren't returned to their reset state before the supply is back up.

[bigmac]

Hello Lundin,

I was not suggesting that there was a problem with normal LVD module operation, upon sag of Vdd level.  Also, under POR conditions, there is no question that there was insufficient Vdd level, for correct MCU operation, otherwise the reset state would have persisted, and no code would have been executed.

The issue here is specifically what happens when the LVD threshold is increased, and the current Vdd happens to be below the new threshold level.  According to the OP there was not an immediate reset, and this did mislead the diagnosis of an inappropriate LVD threshold setting.

I am guessing here, but when increasing the (write once) threshold setting, perhaps there is no effect until the Vdd level firstly exceeds the new threshold.  Excursions of Vdd below the threshold would then trigger a reset, in the normal manner.  However, on the basis of the reported symptoms, there would also appear to be "linkage" to other reset sources, where the LVD reset is also triggered.  I cannot explain the symptoms any other way.

Regards,

Mac