Crystal control clock on the 9s08QB processors

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Crystal control clock on the 9s08QB processors

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SuperDave
Contributor III

I previously posted abut this issue on the Crystal control clock on the 9s08QE processors and provided a solution there but that solution appears not to work correctly for the s08QB8 processors.

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Using a 10 MHz XTAL, External Osc, FEE will work. RDIV= 3 ( div=256 ), Range=1, produces an accurate 39062.5 Hz Reference Clock. This results in a fixed frequency of 40,000,000 Hz from the FLL, and using BDIV=1 ( div by 2 ) produces a 20 MHz bus Clock.

 

With this frequency, the TPM can use the buss clock and achieve the desired accuracy and resolution.

 

Also, using a BDIV=0 can double the frequency but at a cost of higher dissipation.

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When I do this with the QB8, I only get about a 5 MHz bus clock?

Using a 10 MHz xtal ( frequency verified on scope )

 

ICSSC=$FFAE + #$40

ICSC1=#$18   FLL selected, Ext Source, RDIV=256

ICSC2=#$37 BDIV=0, HF=1, HGO=1, ERCLKEN=1,EREFS=OSC

This should produce a 40 Mhz Bus Clock

or

ICSC2=#$77 BDIV=1, HF=1, HGO=1, ERCLKEN=1,EREFS=OSC

This should produce a 20 Mhz Bus Clock

Either way, The BDM reports 4.99 MHZ to a little over 5.01 MHz varies

 

Checking out using TPM:

 

TPMMOD= #$1 ( div by 2 )

TPMSC= #$8 ( Bus Clock used and by 1 )

TPM0SC = #$14 ( Toggle on OVFL )

 

Produces 1.25 MHz

 

Have I overlooked something? It works fine with the QE-32 ( actual values slightly different due to module version differences ).

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david_diaz
NXP Employee
NXP Employee

Hello,

Please note that the Central Processor Unit of the S08QB Series, works up to 20 MHZ as follow:

1.jpg

I assume your application does not work as expected due to the FLL factor corresponding to the DCO frequency range (Table 11-7 - Reference Manual).

2.jpg

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

Freescale does not guarantee the proper behavior of the device out of the ranges mentioned on the datasheet.

In the other hand, the S08QE Series has different operation levels:

3.jpg

Hope this information will be useful for you.

Have an excellent day.

David

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SuperDave
Contributor III

Thanks,

That is actually the issue that we appear to be having, We can not get the bus to run at 20 MHz.

10 MHz bus runs fine but that does not provide the closk output that is needed from the TPM.

I have ordered some chips from a different batch to see if they will work as described.

David

.

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david_diaz
NXP Employee
NXP Employee

Hello,

In case you are referring to the S08QB Series, it is not recommended to set the bus clock at 20 MHZ.

Please note that the Bus clock frequency is one-half of the CPU clock frequency.

If you set the bus clock at 20 MHz implies that the Core is running at 40 MHz which is out of the range.

As I mentioned before, the resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

Hope this information will be useful for you.

Have a great day.

David

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SuperDave
Contributor III

Correction:

ICSC1=#$28   FLL selected, Ext Source, RDIV=1024

Also, when set up this way, it appears that the RTC does not work properly. The RTC is used to update several counters and seems to work ok at lower Bus Clocks but when the Bus Clock is 20 MHz, the system hangs waiting on a counter that does not increment in the RTC routine.

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