ADC Linearity HCS08QB4

[DRichards]

I am using the QB4 ADC with a 5k potentiometer across the supply and its tap to ADP0. The response is not as linear as I had hoped (see attached file).

I have tried different clocks, clock rates, number of bits (10 or 12) fast or low power setting, and all results are practically identical to the one shown. Is this as good as I can expect from this arrangement? I can linearise the response using a look-up table, but would the response vary from device to device?

Pot Readings 5k 12-bit.zip

Message Edited by t.dowe on 2009-09-04 02:02 PM

[DRichards]

I have measured the output voltage of the pot with a DMM and the curve precisely matches that obtained from the ADC (see attached). The implication is that the ADC is measuring accurately, but that the linearity is being affected either by the pot or by the source impedance. My feeling due to the magnitude of the deviation is that it is an effect of the source impedance , although I have tried a 10k pot and the response was slightly better. Is anybody familiar with this behaviour and knows a solution?

Pot_Readings_5k_DVM.zip

Message Edited by t.dowe on 2009-09-04 02:03 PM

[bigmac]

Hello,

Have you properly set the pin control register to disable the I/O circuitry at the pin?  If not, it might be possible that the pin pull-up current is affecting the ADC results.

Regards,

Mac

[PeterHouse]

You could try inserting a buffer amplifier to decrease the source impedance seen by the ADC or ofr this simple test, you could plave a relatively large capacitor on the output of the pot - beware of using a capacitor with large leakage and too much source impedance although I do not think this would be an issue with 100uF and a 5K pot.

Are you trying to use the pot for position sensing or just testing the ADC?  For position sensing, if you really need 10 bit acuracy you will need to calibrate the pot using a lookup table or maybe get a better pot.  There are pots made for position sensing and they are expensive due to the manufacting tolerances.

Good Luck,

Peter House

[DRichards]

bigmac,

I have turned of the port I/O using the supplied macro.

   APCTL1_ADPC0  = 1; //Pot
 

PeterHouse,

    I am using the pot for position sensing. Ignoring two end positions where there is no change, there are 25 detent positions that I need to discriminate between. That is less than 6-bit accuracy required, but the magnitude of the linearity and variation between samples means at the moment that I cannot guarantee that!

Adding a buffer amplifier is a no-go as this is a commercial product that cannot bear that cost.

There is currently a 100nF cap from the wiper to ground. I do get some noise variation on the readings but this is not an issue as its small compared to the accuracy required. There is an underlying non-linearity which at the moment I don't know if it's a loading issue or the pot itself. I will remove the pot from the board and make some resistance measurements in isolation.

[DRichards · Accepted solution]

From my tests, it is now obvious that the problem lies with the potentiometer. I have taken resistance readings between the terminals at all detent settings and the curve derived closely matches those obtained from the DVM and the ADC.

Thanks for your help, it's good to know the chip isn't at fault.

[PeterHouse]

Most likely, the pot you are using is to blame and is a result of mechanical and resistive coating issues.

Are you measuring the input voltage with a voltmeter?  This would be a far  more accurate test.

Make sure your voltmeter is capable of measuring and displaying the 12 bit resolution.   Most cheap ones are not up to this task.  Generally for a measurement like this to accurately test the ADC, you will need about 10x the resolution or an additional 3 1/2 bits or 16 bits of effective resolution to test the calibration of your ADC.  You will also need to use techniques to minimize the effects of noise.

Good Luck,

Peter House