9S08DZ60 - About MCG and CGM configuration

Sangram · ‎07-27-2007

Hello All,

Can you suggest me steps to configure MCG module in MC9S08DZ60 , which will be effective and give same output as CGM module of MC68HC908AZ60A. I am giving you code for CGM module , Crystal frequency used is 8 Mhz.

/****************************************************/

    PCTL=0x00; //PLL out
    PPG=0x26; //PLL for 8MHz
    PBWC=0x80; //AUTOMATIC mode
    PCTL=0x20; //PLL again
       while (PBWC_LOCK ==0 ) // PLL not engaged
    {

      COPCTL=1;         //reset COP counter
     };
     PCTL=0x30;   // PLL switch on

/***************************************************/

I am studying MC9S08 manual. It is having different MCG modes. Very confusing....

I want to write code for MCG module.

Please, guide to do so.

Thanks in advance.

Sangram

--
Alban Edit: FSL Part Number must figure in Message Subject line.

Message Edited by Alban on 2007-07-27 09:17 PM

Sangram · ‎07-30-2007

Hi all,

Can anybody tell me. Is this code ok to switch from FEI to PEE

/**************************************************************/

// (1) On POR MCG is in FEI mode so first switch to FBE mode
        MCGC2 = 0x36;                                      // RANGE = 1 and Crystal is used
                   while(MCGSC_OSCINIT == 1);   //Wait for crystal initialisation
       MCGC1 = 0xB8;                                      //request external reference clock
                  while(MCGSC_IREFST == 1);    //Wait till IRFEST in MCGSC is zero
                  while(MCGSC_CLKST != 2);     //wait till external clock source is selected
       MCGPLL_PLLS = 1;                                //PLL is selected
                  while(MCGSC_PLLST != 1);       //wait till Source of PLLS clock is set to PLL clock.
                   while(MCGSC_LOCK != 1);        //wait for PLL to lock
                                                                        // may be we will clear COP counter here
       MCGC1 = 0x10;                                       // Output of PLL is selected
       MCGC1_RDIV = 2;                                  // R = 4   (2^RDIV)
       MCGPLL_VDIV = 4;                                // M =16   (4*VDIV)
       MCGC2_BDIV= 1;   // B = 2   (2^BIDV) . So,MCGOUT = ((Fext / R) * M ) / B == ((4mHZ/4)*16)/2 =

8mHZ

/************************************************/

cheers

sangram

ramabh · ‎07-30-2007

hi

In the datasheet its clearly mentioned how to switch between the modes with the exact values

If u have any doubts just check example #1 in datasheet this is only when you are using external clock of 4 MHZ and want to have a bus frequency of 8 MHZ

what i want to now is if it fails at one point what to do next?????

Sangram · ‎07-30-2007

Hello,

Yes, i exactly did what is mentioned in example #1 of datasheet. But, thing is that I am suppose to use 8mhz crystal and In FBE mode they clearly says that RIDV should be such that your

Fext / RDIV

result in FBE mode should be between range 32.025 to 39.0625 kHz

Which I think not possible using 8mhz crystal... and RDIV = 2^7= = 128 i.e. 8Mhz/128== 62.5 KHz..

Oops its is not in range... that is where i am confused..

So, is it means we must use crystal of 4 Mhz only or there is any other way to get bus frequency of 4Mhz.

NOTE - See, I am suppose to use PLL as clock source. Crystal of 8 MHz and bus frequency of 4MHz.

I think we should switch in these modes FEI -> FBE-> PBE- >PEE. Correct me if I am wrong..

By the way how to test whether PLL configuration is wrong or not..any test methods you know...

Thanks in advance.

sangram

ramabh · ‎07-30-2007

hi u can use 8 MHZ crystal

but for this you have to go to BLPE mode also

This is the way you have to proceed

FEI ->FBE ->BLPE -> PBE ->PEE

For your refrence i pasted the process how to get 8MHZ Bus clock

The following code sequence describes how to move from FEI mode to PEE mode until the 8MHz crystal

reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in FEI mode out of

reset, this example also shows how to initialize the MCG for PEE mode out of reset.

1. First, FEI must transition to FBE mode:

a) MCGC2 = 0x36 (%00110110)

– BDIV (bits 7 and 6) set to %00, or divide-by-1

– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range

– HGO (bit 4) set to 1 to configure external oscillator for high gain operation

– EREFS (bit 2) set to 1, because a crystal is being used

– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active

b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit

has been initialized.

c) Block Interrupts (If applicable by setting the interrupt bit in the CCR).

d) MCGC1 = 0xB8 (%10111000)

– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock

source

– RDIV (bits 5-3) set to %111, or divide-by-128.

NOTE

8MHz / 128 = 62.5 kHz which is greater than the 31.25 kHz to 39.0625 kHz

range required by the FLL. Therefore after the transition to FBE is

complete, software must progress through to BLPE mode immediately by

setting the LP bit in MCGC2.

– IREFS (bit 2) cleared to 0, selecting the external reference clock

e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current

source for the reference clock

f) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference

clock is selected to feed MCGOUT

2. Then, FBE mode transitions into BLPE mode:

a) MCGC2 = 0x3E (%00111110)

– LP (bit 3) in MCGC2 to 1 (BLPE mode entered)

NOTE

There must be no extra steps (including interrupts) between steps 1d and 2a.

b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR).

c) MCGC1 = 0x98 (%10011000)

– RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1

MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV

does not matter because both the FLL and PLL are disabled. Changing them only sets up the

the dividers for PLL usage in PBE mode

d) MCGC3 = 0x44 (%01000100)

– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the

MCG for PLL usage in PBE mode

– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1MHz reference * 16 = 16 MHz.

In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is

disabled. Changing them only sets up the multiply value for PLL usage in PBE mode

e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS

clock is the PLL

3. Then, BLPE mode transitions into PBE mode:

a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode

b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock

4. Last, PBE mode transitions into PEE mode:

a) MCGC1 = 0x18 (%00011000)

– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the

system clock source

– Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is

selected to feed MCGOUT in the current clock mode

b) Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16,

MCGOUT = [(8 MHz / 8) * 16] / 1 = 16MHz, and the bus frequency isMCGOUT / 2, or 8 MHz

Hope so this example will solve all your questions

Sangram · ‎07-30-2007

Hello,

Thanks for your help. But, I read something which makes all thoughts useless.

Please, read in same datasheet

8.4.6 External Reference Clock

The MCG module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz

in all modes. When ERCLKEN is set, the external reference clock signal will be presented as

MCGERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference

clock will not be used by the FLL or PLL and will only be used as MCGERCLK. In these modes, the

frequency can be equal to the maximum frequency the chip-level timing specifications will support (see

the Device Overview chapter).

which seems ok Because, if we calculate

Max. frequency FLL supports is 39.0625 kHz and Max. RDIV value is 2^7 = 128.

So Fext = 39.0625 * 128 * (10^3) = 5 Mhz.

So, I was thinking in correct way. It must be 4 Mhz or 5Mhz

What is your opinion

Waiting for your reply.

Sangram

ramabh · ‎07-30-2007

what ever you mentioned is there in datasheet.

But what ever i mentioneed is correct as this is what we got from freescale people only.

You donot worry about that FLL clock just follow the procedure that i sent to you.

The example that i copied to you earlier is from their new datasheet only may be that new datasheet is not available in the net.

Sangram · ‎07-30-2007

Hello,

If you are so confident about it , then I will. But, will you please send me the new datasheet.

So, that I can conveince myself.

Yes , I was reading from

MC9S08DZ60 Series Datasheet, Rev 1Draft E

They sat it PRELIMINARY

Subject to change.

Is that mean this datasheet is changed.

Have you work out the PLL. How do you test that it is generating correct bus frequency ?

Now, I am starting code as per you suggestions. But, waiting for your datasheet.

Thanks in advance,

Cheers.

Sangram

Alban · ‎07-30-2007

Hello,

Here is a link to the page of latest DZ datasheet:
http://www.freescale.com/S08D

S08DZ Datasheet:
http://www.freescale.com/files/microcontrollers/doc/data_sheet/MC9S08DZ60.pdf?tid=t8DZlp2

Cheers,
Alban.

ramabh · ‎07-30-2007

Hi

what ever latest datasheet that alban mentioned doesnot contain PLL latest settings

Here i am attaching the latest one

--
Alban Edit: Removed NDA Required document

Message Edited by Alban on 2007-07-30 10:54 AM

Alban · ‎07-30-2007

Hello,

Sorry, but you must have not seen that the document you attached says NON DISCLOSURE AGREEMENT REQUIRED.
This means that you are STRICTLY FORBIDDEN to distribute it !!!

I'm looking with FSL Marketing if they have a newer version to put public.
In the meantime, please DO NOT post confidential information !

Cheers,
Alban.

Sangram · ‎07-30-2007

Hello,

Ramabh - Have you executed your code ?

If yes and using the same steps you mentioned in above posts then I will go for it.

Alban : Can you guide us to make it work. Why there is such confusion about FLL and FBE mode.

As per datasheet (Both)

1. First, FEI must transition to FBE mode:

MCGC1 = 0xB8 (%10111000)

– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock

source

– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is

in the 31.25 kHz to 39.0625 kHz range required by the FLL

– IREFS (bit 2) cleared to 0, selecting the external reference clock

In FBE mode itself they mentioned that FLL frequency I/p must be in 31.25khz to 39.0625. kHz

How is it possible then to go to BLPE or directly to PBE mode.

What RAMABH posted is correct or wrong ?

Please, answer these questions.

Best regards

Sangram

Alban · ‎07-30-2007

Hi again,

I received confirmation that the datasheet on the link I gave should be shortly updated to RevK.

Kind Regards,

Alban.

Sangram · ‎07-30-2007

Thank you Alban and ramabh,

But, still Alban my query is unanswered. In sample programs given by you , Fext is 4Mhz. What if it is 8Mhz ? What to choose RDIV in FBE mode ?

Also, correct me if I am wrong. FBE(FLL bypass external). It means we are using external clock for MCGOUT as source and not FLL. Then is it ok in all Bypass mode if we neglect FLL or PLL related bits.

like in PBE , FBE.

Please, clear my doubt and notify me on upadation of new datasheet

Thanks in advance.

Cheers

Sangram

Alban · ‎07-30-2007

Hello Sangram,

You will have to read the datasheet to change the factor 2, it should not be very difficult.

I don't know the module MCG, but the code provided does work and has been tested.

Regards,

Alban.

Sangram · ‎07-30-2007

Hello Alban,

That is what I am trying to tell you. This code is ok for 4 Mhz crystal.

Now, If you have 8 Mhz crystal.

In FBE mode (page 144 topic no 8.4.1.4)

they says that

" RDIV bits are written to devide reference clock to be within the range of 31.25 kHz to 39.0625 kHz "

So, Fext / RDIV = 8 mHz / 128 = 62.5 Khz. which is not in the above range..

and for 4 mHz it is 4 mHz/128 = 31.25 Khz which is in range....Ok...

And as to go to PEE mode we have to come through FBE mode. How come it is possible for 8 Mhz crystal ?

Also , in same document they says on page 147 topic no. 8.4.6

"The MCG module can support an external clock with frequencies between 31.25 Khz to 5 mHz in all modes"

What is your comment on this sentence. Is it means we can select external crystal maximum of 5 Mhz ?

See, right now I dont have compiler to see that it is correct or wrong. But, help from you as moderator is highly appreciated. I am also very much new to PLL and 9S08.. Why do they need these modes and FLL ?

I am reading this document for last 4 days again and again... Help me to come out of this confusing document..

Well ! thanks a lot for being with me. If possible,answer my question ASAP.

Thanks and Best regards

Sangram

ramabh · ‎07-31-2007

hi sangram

Why you are worrying a lot with your 8 MHZ.

As you are using 8 MHZ external crystal only you have to go to BLPE mode otherwise no need to go to that mode directly you can go to PBE.This is the latest information i am having .

And you can even use a 16MHZ external crystal also its not at a problem.

I followed the same procedure that i sent to you and its checked.

or else its better if you wait for their latest datasheets

Alban · ‎07-30-2007

Hello Sangram,
I'm not a S08 expert and the MCG is indeed not the easiest module.
However, the page 151 of the datasheet DraftE exactly answers the question asked in your last post.

I was kindly given some code I can share with you:

FEE Hi Gain Hi Range

Code:

  SOPT1_COPT = 0;   /* disable COP */  SOPT2_MCSEL = 1;  /* enable MCLK. MCLK = BUSCLK/2 */    Ports_Init();    EnableInterrupts; /* enable interrupts */  /* Configure MCG to produce a 16MHz bus clock
from a 4MHz external crystal via FLL */    /* set up external oscillator */    MCGC2_RANGE = 1;  MCGC2_ERCLKEN=1;  MCGC2_EREFS = 1;    MCGC2_HGO = 1;  while (!MCGSC_OSCINIT);    /* Change the reference divider */  MCGC1_RDIV = 0b111;            /* Select Reference Clock */  MCGC1_IREFS = 0;  /* wait for Reference Status bit to update */  while (!MCGSC_IREFST);           /* Wait for LOCK bit to set */  while (!MCGSC_LOCK);    /* Select the Bus Divider */  MCGC2_BDIV = 0b00;    /* Turn on Clock Monitor *///  MCGC3_CME = 1;  MCG_MODE = FEE;

And another piece of code for:

PEE Example of the datasheet 4.0MHz Hi Gain:

Code:

  SOPT1_COPT = 0;   /* disable COP */  SOPT2_MCSEL = 1;  /* enable MCLK. MCLK = BUSCLK/2 */    Ports_Init();    EnableInterrupts; /* enable interrupts */  /* Configure MCG to produce a 20MHz bus clock from a
4MHz external crystal via PLL */    /* Select High Range, High Gain, Bus divided by 1, Oscillator,
ERCLK enabled */  MCGC2 = 0x36;   while (!MCGSC_OSCINIT);    /* Select External Clock as bus clock source,
Reference divided by 8, Reference = external */  MCGC1 = 0xB8;     /* wait for Reference Status bit to update */  while (!MCGSC_IREFST);         /* Wait for clock status bits to update */  while (MCGSC_CLKST != 0b10);               /* now in FBE mode */            /* Enter BLPE mode *///  MCGC2_LP=1;   /* now in BLPE mode */  /* Change RDIV for PLL reference */  MCGC1 = 0x90;    /* Select the VCO divider and PLL */  MCGC3 = 0x4A;    /* Enter PBE mode *///  MCGC2_LP=0;     /* Wait for PLL status to update */  while (!MCGSC_PLLST);  /* now in PBE mode */    /* Wait for LOCK bit to set */  while (!MCGSC_LOCK);    /* Enter PEE mode */  MCGC1 = 0x10;    /* Wait for Clock status to indicate PLL output */  while (MCGSC_CLKST != 0b11);    MCG_MODE = PEE; /* Switch on Clock monitor */ MCGC3_CME = 1;   /* Enable LOL IRQ */ MCGC3_LOLIE = 1;

You can use these examples to adapt them to your code.
The second one is a reproduction from the datasheet.

I hope you will find these useful.

Kind Regards,
Alban.

9S08DZ60 - About MCG and CGM configuration

9S08DZ60 - About MCG and CGM configuration

General