LS1043 DDR4 Routing Guidelines

johnf95037 — Tue, 19 Jan 2021 02:58:19 GMT

I'm looking for timing constraints for routing discrete DDR4. DQS to DQ and DQM, DQS to CLK, and CLK to address and control. Does such a document exist?

Thanks,

-j

Re: LS1043 DDR4 Routing Guidelines

johnf95037 — Thu, 21 Jan 2021 05:13:40 GMT

I see timing in the datasheet and references to write leveling in the reference manual, but nothing that puts it all together. This is a mature processor, there must be some documentation describing the timing requirements so I can put together my layout constraints.

Anything? TI, Xilinx and Synopsys have such information.

Thanks,

-j

Wireless MCU中的主题 LS1043 DDR4 Routing Guidelines

LS1043 DDR4 Routing Guidelines

Re: LS1043 DDR4 Routing Guidelines