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    <title>Vybrid Processors中的主题 Re: Interfacing SPI with vF5xx processor</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248188#M910</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, thanks. I will check internally.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 21 Feb 2014 21:40:27 GMT</pubDate>
    <dc:creator>karina_valencia</dc:creator>
    <dc:date>2014-02-21T21:40:27Z</dc:date>
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      <title>Interfacing SPI with vF5xx processor</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248185#M907</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi I am&amp;nbsp; planning to use MVF51NS151CMK50 vybrid processor and I have four SPI based devices. One is wifi module which communicates via spi and has 4 data bit signals. Other 3 are RTCs and EEPROM . Please let me know the necessary pin details to interface with the processor. I have referred the data sheet and I could see DSPI. Can you get me some application notes about DSPI and how it is different from standard SPI. Does freescale has any reference designs available for vybrid controllers. It will be very helpful for me to understand if you can share any reference designs.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Feb 2014 12:53:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248185#M907</guid>
      <dc:creator>ramakrishna</dc:creator>
      <dc:date>2014-02-20T12:53:03Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing SPI with vF5xx processor</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248186#M908</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/timesyssupport"&gt;timesyssupport&lt;/A&gt; can you attend this case?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Feb 2014 16:38:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248186#M908</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2014-02-21T16:38:45Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing SPI with vF5xx processor</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248187#M909</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Timesys provides support for the VF6xx platform. This question may be better intended for the Freescale design team.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Feb 2014 20:34:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248187#M909</guid>
      <dc:creator>timesyssupport</dc:creator>
      <dc:date>2014-02-21T20:34:08Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing SPI with vF5xx processor</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248188#M910</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok, thanks. I will check internally.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Feb 2014 21:40:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248188#M910</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2014-02-21T21:40:27Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing SPI with vF5xx processor</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248189#M911</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"&gt;Hello &lt;/SPAN&gt;Rama,&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Both vF5xx and vF6xx have the same number of DSPI interfaces.&lt;/LI&gt;&lt;LI&gt;Generally speaking, Vybrid's pins are shared among various interfaces; to demonstrate in a reference design how a specific interface operates, it is enough to have 1 of them; having more demonstrates nothing new compared to 1 but "steals" pins from the other interfaces, which should be demonstrated, too.&lt;/LI&gt;&lt;LI&gt;The SPI interface &lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;is described in detail in the Vybrid Reference Manual (can be found on our web site).&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Sincerely yours, Naoum Gitnik.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;DIV class="js-thread-post-wrapper j-rc4 j-thread-post-wrapper jive-content"&gt;&lt;DIV class="j-thread-post j-rc4"&gt;&lt;DIV&gt;&lt;A _jive_internal="true" class="jiveTT-hover-user jive-link-profile-small" data-containerid="-1" data-containertype="-1" data-objectid="214905" data-objecttype="3" href="https://community.nxp.com/people/timesyssupport"&gt;Timesys Support&lt;/A&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Feb 2014 23:55:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Interfacing-SPI-with-vF5xx-processor/m-p/248189#M911</guid>
      <dc:creator>naoumgitnik</dc:creator>
      <dc:date>2014-02-21T23:55:30Z</dc:date>
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