topic Re: Parallel QuadSPI in Vybrid Processors

Parallel QuadSPI

anthony_huereca — Thu, 27 Jun 2013 20:26:20 GMT

We've been helping one of our alpha customers with using QuadSPI in parallel mode on Vybrid, so I wanted to create a thread about some helpful tips when trying to do the same. There will be a parallel mode booting example in the next release of the sample code.

Vybrid has two QuadSPI modules: QuadSPI0 and QuadSPI1. QuadSPI0 then has two QuadSPI ports associated with it: QuadSPI0_A and QuadSPI0_B. This lets you use the QuadSPI flashes connected to those ports in parallel. QuadSPI1 only has one port, and thus parallel mode cannot be used with it. So in summary, there are two modules on Vybrid, capable of interfacing with up to 3 flashes in all, but only QuadSPI0 can do parallel mode.

Parallel mode is enabled by setting QuadSPI_BFGENCR[PAR_EN]=1. When set, the data at offset 0x200 of each QuadSPI would be read at offset 0x400 when combined. This is very important to keep in mind when programming data into each flash.

Each flash in parallel mode holds a nibble (4 bits) of data from each byte. The way that data is split is a somewhat complicated, and so it's very important to properly split the data that ends up being programmed in each of the two flashes. The sample code contains a function split() which does this a word (2 bytes) at a time. The code is attached. It takes a source memory address, and outputs each half into the two destination memory addresses.

After programming the flashes, put the QuadSPI into parallel mode, and make sure the data you read back from the memory window matches what you think you should have. This will double check your programming and splitting algorithms.

Parallel Booting:

The QuadSPI boot header must be programmed into only *one* flash connected to QuadSPI0_A. The BootROM reads this configuration data, and only then puts the QuadSPI in parallel mode. So all other boot data and code after that must be programmed as if being read in parallel mode. What this ends up meaning is that you need three programming passes:

Program the QuadSPI boot header into QuadSPI0_A flash at offset 0x0
Program the split data starting at offset 0x200 (per the sample code) into QuadSPI0_A
Program the split data starting at offset 0x200 (per the sample code) into QuadSPI0_B.

The sample code will show this being done.

There are only a few minor changes in the QuadSPI boot header necessary.

Set the "Parallel Port Enable" field
Make sure the "Flash B1 Size" field is properly sized
Make sure the "Port B Enable" field is set

There should be no other code changes necessary if you already have single QuadSPI flash boot working.

Debugging Tips:

Make sure the data read back in parallel mode when you program the flashes match the binary you're trying to boot (except for the boot header section, which will look incorrect when read in parallel mode since it was only programmed into the single QuadSPI0_A flash).
Make sure the code works in single flash mode still
Make sure your IO Mux config isn't turning off the QuadSPI0_B pins.
As with any boot debugging, try turning on an LED as one of the very first instructions. If you reach there, showing you did boot successfully, then keep moving it back through your code until you find the spot it crashes on.

Original Attachment has been moved to: split.c.zip

Re: Parallel QuadSPI

kef2 — Fri, 07 Mar 2014 13:38:31 GMT

Hello Anthony,

I have few questions regarding parallel QSPI0 mode.

1) Provided there is only one A_CS0 chip and one B_CS0 chip of the same size, what would be right SF??AD registers settings for parallel and not parallel modes. Vybrid RM Rev5. Figure 30-419 doesnn't explain what settings should be made when CS1 chips are not installed. According to picture SFA2AD shoud be set = 0x20000000 + chip A size + chip B size. And SFB2AD = SFA2AD. And SFA1AD and SFB1AD don't matter?

For not parallel mode I think it should be like this and work for every set of chip memory size:

SFA1AD = 0x20000000 + chip_a1_size;

SFA2AD = 0x20000000 + chip_a1_size + chip_a2_size;

SFB1AD = 0x20000000 + chip_a1_size + chip_a2_size + chip_b1_size;

SFB2AD = 0x20000000 + chip_a1_size + chip_a2_size + chip_b1_size + chip_b2_size;

What should these lines look like for parallel mode?

2) Table 30-427 Instruction set mentions 2'd3 - Eight pads mode. How does this pads mode work? Does it work in not_/parallel mode only? Does it enable both A and B chip selects?

3) I wonder how should I issue QSPI memory program commands in parallel mode. Trying to write in parallel mode, I'm getting IUEF error:

IP Command Usage Error Flag: Set when in parallel flash mode the execution of an IP Command is started with more than one pad enabled and the sequence pointed to by the sequence ID contains a WRITE or a WRITE_DDR command. Refer to Table 30-427 table for the related commands. No communication with the serial flash device is initiated by the QuadSPI module.

Should "and" in bold above be read as "or"? If so, then I need to interleave data nybbles in software and program A chip, and then B chip, right?

Re: Parallel QuadSPI

anthony_huereca — Fri, 07 Mar 2014 14:00:20 GMT

Hi Edward,

For your first question, take a look at the Vybrid sample code in the \src\drivers\quadspi and \src\projects\quadspi_load projects for examples of how to setup the QuadSPI. Those values do not change when the QuadSPI is being accessed in parallel mode, since those registers are used to help define how big each flash is. The QuadSPI module takes care of all the mapping for you so you don't have to. It's just a big memory block at the end of the day. You'll notice in the code that entering parallel mode doesn't modify the register values except for QuadSPI_BFGENCR[PAR_EN]=1

For the second question, that's a typo in the RM. If you look at the register definition for QuadSPIx_LUTn in section 30.32.32 you'll see that the value of 2'd3 is not valid. Basically in parallel mode the LUT entry will not change. The parallel enable bit tells QuadSPI0 to read both flashes and combine the data together to do the read. How those flashes are read at the LUT level does not change though.

For your last question, you cannot write in parallel mode. You have to write each flash individually, and the C file attached to the post, and the quadspi_load project, provide an example of how to do this to properly. The interleaving isn't totally straight forward, hence the function provided.

Re: Parallel QuadSPI

jackblather — Fri, 07 Mar 2014 20:47:19 GMT

Hi Anthony,

I looked at the \src\drivers\quadspi and \src\projects\quadspi_load directory and it has a file quadspi_load.h, but it is blank. Was this file supposed to be empty?

I want to run this example under DS-5 in Ubuntu. Will that example work in DS-5/Ubuntu? I see the "#ifdef ARMCC_A5" in quadspi_load.c, but I'm wondering if there are differences between DS-5/Windows and DS-5/Ubuntu that will prevent this example from working.

Thanks.

Re: Parallel QuadSPI

kef2 — Sat, 08 Mar 2014 14:45:16 GMT

Hi Anthony,

Thanks for your reply, it is clear now that WRITE and WRITE_DDR LUT commands can't be used in parallel mode. It is possible to read status register in parallel, program QUAD bit in parallel or set write protection on/off in parallel, but memory program has to be performed with IP_EN=0, splitting nibbles with code like in your split.c.

Data write to both channels in parallel still can be done, but only to send constants programmed in LUT, like this:

LUT for program Spansion QUAD bit should look like this:

CMD - one_pad - 0x01

CMD - one_pad - 0x00

CMD - one_pad - 0x02

LUT for enable Spansion advanced sector protection (DYB) like this:

CMD - one_pad - 0xE1

ADDR - one_pad - 32

CMD - one_pad - 0

Regards

Re: Parallel QuadSPI

nancyb — Fri, 25 Jul 2014 14:01:12 GMT

Is there a viable example project implementing parallel QuadSPI? I checked VybridSampleCode download and the last update was last year. I am currently using the quadspi_load project to flash QuadSPI on a Vybrid Tower board.

I am very interested in demonstrating parallel QuadSPI for our product and would like to leverage from a working example.

Regards,

Nancy Burkholder

Re: Re: Parallel QuadSPI

anthony_huereca — Fri, 25 Jul 2014 16:35:02 GMT

Hi Nancy,

See the attached quadspi_load.c file which can overwrite the current one in the SC. The split() function is in the file attached to the original post. That should work then for you.

To use parallel mode, change #define PARALLEL_MODE to 1 in quadspi_load.c

You will also need to modify \src\boot\quadspi\quadspi_boot.c to enable the parallel boot option:

1, //Parallel Port Enable (0=disabled, 1=enabled)

Re: Parallel QuadSPI

nancyb — Tue, 29 Jul 2014 12:48:51 GMT

Hi Anthony,

I updated my quadspi_load project to use your quadspi_load.c and split.c. I added the following #defines to quadspi_load.c

#define PARALLEL_MODE 1

#define FLASH1_BASE_ADR 0x20000000

#define FLASH2_BASE_ADR 0x21000000

In source file quadspi.c I modified quadspi_erase( void ) to quadspi_erase( unsigned long address ) in order to work with your code in main(). I did not modify any other quadspi code in Vybrid Sample Code folder.

I modified quadspi_conf in the hello_world example code:

...

1, /* Parallel Mode Disable */

...

The image would not boot when I configured the jumpers to boot from QSPI. I could debug the image executing in QSPI through IAR EW IDE and j-link. I stepped through the image and verified it was executing from QSPI.

I am continuing to investigate.

Regards,

Nancy

Here is the hello_world quadspi_conf:

const SFLASH_CONFIGURATION_PARAM quadspi_conf = {

0, /* DQS LoopBack */

0, /* Reserved 1*/

0, /* Reserved 2*/

0, /* Reserved 3*/

0, /* Reserved 4*/

0, /* cs_hold_time */

0, /* cs_setup_time */

0x400000, /* A1 flash size */

0, /* A2 flash size */

0, /* B1 flash size */

0, /* B2 flash size */

0, /* SCLK Freq */

0, /* Reserved 5*/

1, /* Single Mode Flash */

0, /* Port - Only A1 */

0, /* DDR Mode Disable */

0, /* DQS Disable */

1, /* Parallel Mode Disable */

0, /* Port A CS1 */

0, /* Port B CS1 */

0, /* FS Phase */

0, /* FS Delay */

0, /* DDR Sampling */

/* LUT Programming */

0x0403,

0x0818,

0x1c08,

0x2400,

};

Re: Parallel QuadSPI

nancyb — Tue, 29 Jul 2014 13:15:10 GMT

I tried using my quad mode quadspi_conf. I can run the image from the IAR debug session but the processor won't boot the image otherwise.

Nancy

#define SCLK 1

const SFLASH_CONFIGURATION_PARAM quadspi_conf = {

0, /* DQS LoopBack */

0, /* Reserved 1*/

0, /* Reserved 2*/

0, /* Reserved 3*/

0, /* Reserved 4*/

0, /* cs_hold_time */

0, /* cs_setup_time */

0x1000000, /* A1 flash size */

0x1000000, /* A2 flash size */

0x1000000, /* B1 flash size */

0, /* B2 flash size */

SCLK, /* SCLK Freq */

0, /* Reserved 5*/

4, /* Quad Mode Flash */

0, /* Port - Only A1 */

0, /* DDR Mode Disable */

0, /* DQS Disable */

1, /* Parallel Mode Enable */

0, /* Port A CS1 */

0, /* Port B CS1 */

0, /* FS Phase */

0, /* FS Delay */

0, /* DDR Sampling */

/* LUT Programming */

0x046B, // CMD QOR

0x0818, // ADDR 24

0x0C08, // DUMMY 8

0x1E80, // READ (4) 0x80

0x2400, // JMP_CS 0

0x0000, // STOP

};

Re: Parallel QuadSPI

kef2 — Tue, 29 Jul 2014 18:49:24 GMT

Nancy,

quadspi_conf has to be programmed in nonparallel mode to CS0 chip (or, if you wish, the same nonparallel copy to both CS0 and CS1 chips). I don't know how others are doing it, I defined few macros, which replace byte 0x12, with two bytes 0x11,0x22, which helps putting the same nonparallel copy of quadspi_conf to both chips.

#if QSPI_PARALLEL
#define w8(x) (((x) & 0xF0) >>4) * 0x11, ((x) & 0x0F) * 0x11
#define w16(x) w8(x), w8((x) / 256u)
#define w32(x) w16(x), w16((x) / 65536ul)
#else
#define w8(x) :smileyx:
#define w16(x) ((x)&0xFF), ((x) / 256u)
#define w32(x) w16(x), w16((x) / 65536ul)
#endif

const char quadspi_conf0[0x400] =
{
   w32(0),                      /* Reserved (DQS LoopBack) */
   w8(3),                       // hold delay B, A (BA) enable 00/01/10/11
   w8(0),                       // half speed phase sel. 0 - at non-inv clock, 1 - at inv clock
   w8(0),                       // half speed delay selection 0- one cycle delay, 1-two clock cycle delay
   w8(0),                       /* reserved 1*/
   w32(0),w32(0),w32(0),        /* Reserved 2-4*/
   w32(3),                      /* cs_hold_time, serial clocks */
   w32(3),                      /* cs_setup_time, serial clocks */
   w32(QSPI_MEM_A1_SZ),         /* A1 flash size */
   w32(QSPI_MEM_A2_SZ),         /* A2 flash size */
   w32(QSPI_MEM_B1_SZ),         /* B1 flash size */
   w32(QSPI_MEM_B2_SZ),         /* B2 flash size */

   w32(      0*0                /* SCLK Freq 18MHz */
     | 1*0                // 60MHz
     | 2*0                // 74MHz
     | 3*1                // 99MHz
),
   w32(0),                      /* Reserved 5*/

w8(PINMODE), /* Single Mode Flash 1/2/4 pads*/

   w8(QSPI_MEM_B1_SZ || QSPI_MEM_B2_SZ), /* 0 - port B used, 1- port B not used */
   w8(1*0),                    /* DDR Mode Enable */
   w8(1*0),                    /* DQS strobe enable */
   w8(!!QSPI_PARALLEL),        /* Parallel Mode enable */
   w8(!!QSPI_MEM_A2_SZ),       /* CS1 on port A enable*/
   w8(!!QSPI_MEM_B2_SZ),       /* CS1 on port Benable*/
   w8(0),                      /* FS Phase - 0 - sample at non-inv. clock, 1 - at inv. clock*/
   w8(0),                      /* FS Delay - 0 - 1clk, 1- 2clk*/
   w8(0),                      /* DDR Sampling selay 0..7*/
/* LUT Programming */
#if PINMODE==1 // 1-pin
   w16( LUTi0(lCMD,pOne,0x3) ),
   w16( LUTi0(lADDR,pOne,24) ),
   w16( LUTi0(lREAD,pOne,8) ),
   w16( LUTi0(lJMP_ON_CS,pOne, 0) ),
   w16( LUTi0(0, 0, 0)             ),
#elif PINMODE==4 // 4-pin
   w16( LUTi0(lCMD,pOne,0xEB) ),
   w16( LUTi0(lADDR, pFour, 24) ),
   w16( LUTi0(lMODE,pFour,0x55) ),                 // 0xAx - skip CMD
   w16( LUTi0(lDUMMY, pFour, 4) ),
   w16( LUTi0(lREAD,pFour,8) ),
   w16( LUTi0(lJMP_ON_CS, pOne, 0) ),              // 1 skip CMD if mode is 0xA*
   w16( LUTi0(0, 0, 0) ),
   w16( LUTi0(0, 0, 0) ),
#endif
};

Re: Parallel QuadSPI

nancyb — Thu, 31 Jul 2014 15:59:35 GMT

Edward,

Thank you for sharing your configuration. I borrowed some of your values and plugged them into my project, along with the code supplied by Anthony, and was able to successfully flash, boot, and execute the Vybrid Sample Code "hello_world" image. While stepping through the code (IAR and j-link) I observed the QuadSPI0_BFGENCR bit PAR_EN set to 1.

I have not yet successfully translated this success to my MQX application but it is nice to have a working example.

Nancy

Re: Parallel QuadSPI

nancyb — Tue, 19 Aug 2014 15:13:06 GMT

I am having trouble creating a bootable MQX QSPI image in parallel mode.

I have two test images: hello_world from the Vybrid sample code and hello2 from MQX examples. I am using the Vybrid Tower platform, IAR 7.2 Embedded Workbench, and j-trace debugger pod.

I modified the Vybrid sample code program quadspi_load to support flashing an image in parallel mode using split.c, modified quadspi_load.c, and related QuadSPI configuration parameters as noted in earlier thread entries.

I can reliably flash hello_world and boot in parallel mode; no problems at all.

I can build, flash and boot hello2 in QSPI single mode but the image will not boot in parallel mode.

I have discovered that after exiting quadspi_load debug, and without changing the board jumpers or cycling power, I can connect the debugger to the target using the hello2 QSPI debug configuration. Then I can reset the debugger and execution starts at __boot at 0x20000800. Thereupon the MQX image will run in parallel mode without problem.

I verified that hello_world and hello2 use identical QuadSPI configuration parameters and IVT. The QuadSPI configuration parameters are programmed in single mode and the reset of the image is programmed in parallel mode.

Is there some other configuration required for MQX that I have overlooked that would allow the single mode image to boot and derail the parallel mode boot?

Re: Parallel QuadSPI

kef2 — Wed, 20 Aug 2014 06:41:54 GMT

Nancy,

I guess you are booting MQX code, which executes from QSPI? If so, then perhaps MQX initializes QSPI and at some point CPU is unable to read some instructions. You could try disabling QSPI, rebuilding MQX and see if it helps. QSPI still can be reinitialized while executing from QSPI, but it should be done executing from RAM or DDR or some other unaffected memory. If there are some interrupt handlers in QSPI memory, then QSPI reinitialization should be done with interrupts disabled.

Also you may try debugging MQX from start point. Don't know about IAR, but DS-5 has hardware breakpoints, which can be set in QSPI and load_debugger_symbols without loading code. After QSPI programming one needs to reset from debugger, so that PC points to 0, set HW breakpoint at MQX entry point and hit run. Debugger should stop where it is asked for.

Re: Parallel QuadSPI

nancyb — Fri, 22 Aug 2014 12:58:02 GMT

Hi Edward,

My executable image using MQX is built for QSPI XIP and the Vybrid boot ROM handles the QSPI device initialization using the QuadSPI configuration values.

I build the MQX image for single mode and Vybrid boots XIP without issue. I can connect the debugger and step/run without exception.

I build the MQX image for parallel mode and Vybrid goes off into the weeds. Nothing gets initialized and the debugger cannot connect.

The only difference between an MQX image that works and fails is building the image for QuadSPI parallel mode.

I have verified that QuadSPI configuration values and the IVT are valid because I use the same values to run the non-MQX hello_world image.

I am at a loss to explain why my MQX image built for QuadSPI parallel mode fails to boot XIP.

Nancy

Re: Parallel QuadSPI

kef2 — Fri, 22 Aug 2014 13:58:17 GMT

Hi Nancy,

I guess you have MQX configured to enable / initialize QSPI at reset. I guess it MQX is configured to initialize QSPI for non-parallel mode. That's one possible problem. Even if MQX was configuring QSPI for parallel mode, the same like it is specified in QPSI boot config tables, reinitialization of QSPI still may make your code jumping into the weeds. It is the same like destroying a bridge, on which you are at the moment. Will it hang or not depends on many factors. So I'm asking (again), did you try to disable QSPI in MQX BSP? I'd try it.

> I build the MQX image for parallel mode and Vybrid goes off into the weeds. Nothing gets initialized and the debugger cannot connect.

Perhaps you can't debug using Keil, but it is possible to debug using DS-5. Hit reset button in debugger, which is set up to not start and go until main() or other function, set HARDWARE breakpoint, hit run.

Regards

Edward

Re: Parallel QuadSPI

nancyb — Fri, 22 Aug 2014 14:58:17 GMT

Hi Edward,

I verified that the MQX QuadSPI and QuadSPI FlashX drivers are disabled in user_config.h and the BSP has been built with this setting.

I didn't think the MQX BSP would be an issue because the debugger stops at the first instruction in the image prior to starting MQX.

I set up my j-Trace with hardware breakpoints but the debugger reports failure to temporarily halting the CPU for reading CP15 register when I try to connect to the target. If I continue rather than abort the debugger I cannot perform any operations.

It seems to me that if the QuadSPI configuration parameters and IVT are valid then the ROM boot code would proceed with a viable QuadSPI boot. I can observe this behavior with my non-MQX image built for parallel mode and with my MQX image built for single mode.

I appreciate your suggestions and insight into how I can proceed.

Nancy

Re: Parallel QuadSPI

kef2 — Mon, 25 Aug 2014 07:05:32 GMT

Hi Nancy

How do you program image to flash? Are you using quadspi_load? I'm not sure, but I think I saw bug in quadspi.c quadspi_program() function. I think it didn't program last sector of image, in case it wasn't complete and not sector address aligned. I'm not sure about it, but you should check if whole image is programmed properly. There should be no difference between MQX program and bare metal program, both should run well in parallel mode.

I didn't think the MQX BSP would be an issue because the debugger stops at the first instruction in the image prior to starting MQX.

After code runs away, debugger may point to any location.

You should not worry about connection problems here. Debugger still should allow you to reset target so that PC register points to 0x0 address. Then you should set HW breakpoint to entry point and hit Run. Target CPU should execute boot ROM code, and if QSPI config is OK, debugger should stop at entry point, of course if boot ROM reads QSPI config and all tables properly and makes a jump to proper address.

Does your project include some IP? If not, perhaps I could try compiling it and see what's wrong.

Edward

Re: Parallel QuadSPI

nancyb — Mon, 25 Aug 2014 13:54:52 GMT

Hi Edward,

I use quadspi_load to flash QuadSPI. My version of quadspi_load defines size at 0x40000, which is much larger than the MQX image size of 0xed3c. Next time I run quadspi_load I will observe quadspi_program() to see how it handles the size.

The test images do not have any IP issues. They are example code that I was using to test my modifications of quadspi_load to handle parallel QuadSPI.

Nancy

Re: Parallel QuadSPI

nancyb — Mon, 25 Aug 2014 14:02:26 GMT

For some reason I cannot post my original response; the website keeps reporting an error and will not save my reply. I am using Chrome but the same error happens using IE.

Nancy

Re: Parallel QuadSPI

nancyb — Mon, 25 Aug 2014 14:03:36 GMT

One curious observation: When I exit quadspi_load after flashing my MQX image to QuadSPI, and without altering the boot configuration or resetting the target, I can connect back to the target using the MQX hello2 XIP image. Then I can pause the processor and observe it running the endless loop from quadspi_load. When I issue a reset command then execution stops at 0x20000800. From that point I can step through the MQX image and the MQX image executes without issue. The trouble begins when I set the boot configuration for QuadSPI and power cycle the target. The image fails to boot and I cannot connect the debugger.