topic Re: How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor. in Vybrid Processors

How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor.

Lyuda — Wed, 16 Apr 2025 14:23:41 GMT

Hello

I use the dspi0 on my board which connects to the Intel_ALTERA 10M08SCU169C8G chip.
Fragment from the devices tree which I have at the moment:

&edma1 {
status = "okay";
};

&dspi0 {
bus-num = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi0>;
status = "okay";

/*sflash: at26df081a@0 {*/
spidev0: spidev@0 {
/*#address-cells = <1>;*/
/*#size-cells = <1>;*/
/*compatible = "atmel,at26df081a";*/
compatible = "toradex,evalspi";
/*spi-max-frequency = <16000000>;*/
spi-max-frequency = <66000000>;
/*spi-cpol;*/
/*spi-cpha;*/
reg = <0>;
};
};

pinctrl_dspi0: dspi0grp {
fsl,pins = <
VF610_PAD_PTB19__DSPI0_CS0 0x1182
VF610_PAD_PTB20__DSPI0_SIN 0x1181
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
VF610_PAD_PTB22__DSPI0_SCK 0x1182
>;
};

I want to get spi-max-frequency 66 MHz but I get only 16 MHz.
How can I get frequency above 16 mhz?

My board uses Linux for TWR-VF65GS10.

Thanks.

Re: How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor.

JosephAtNXP — Thu, 17 Apr 2025 00:28:46 GMT

Hi,

Thank you for your interest in NXP Semiconductor products,

Please consider the clock rate assignment, the PLL might be divided and can't reach the frequency specified, be sure to have a clock rate 4x the 66 MHz.

Regards

Re: How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor.

Lyuda — Thu, 17 Apr 2025 21:12:58 GMT

Hi
Thanks for the answer.

Why do i need to multiply by 4 and not by 2?

SCK baud rate = (fp/PBR) x [(1+DBR)/BR].
It is written in the section "12.4 Serial Peripheral Interface (SPI)" of the VFXXXRM.pdf document.
Min PBR = 2, min BR = 2. At DBR = 0 SCK baud rate = fp/4 and at DBR = 1 SCK baud rate = fp/2

Can I multiply by 2 The prescaled clock?

Re: How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor.

Lyuda — Sun, 20 Apr 2025 13:41:24 GMT

Hi JosephAtNXP

At the moment I want to find out what maximum frequency the MVF61NN151CMK50 processor can produce.
Maybe one of the users or specialists can answer me.

Here are my thoughts.
The section "6.1.8 Clock Configuration" of the VFXXXRM.pdf document says the following:
"For other modules on this device, the register interface work at the IPS clock frequency,
which is half of Platform Bus clock. For example:
• DAC
• PDB
• PIT
• LPTMR
• SPI
• I2C
• UART
• LCD
• VIU"

We find the maximum frequency for SPI from the table "Table 6-6. Clocking Configuration".
It is equal to 83 MHz. that is fp=83 MHz.
Hence at DBR = 0 SCK baud rate = fp/4 = 20,75 MHz or at DBR = 1 SCK baud rate = fp/2 = 41,5 MHz

Am I right in my thinking?

Re: How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor.

kef2 — Mon, 23 Jun 2025 07:51:23 GMT

You are right, 41.6MHz is max SPI frequency for 500MHz VF61. Unfortunately Linux driver seems not supporting double bit rate (DBR bit), so you are limited to 20.8MHz. Try setting spi-max-frequency to 20000000.

For 40MHz you either need to alter Linux driver or perhaps try using `devmem2` to manipulate DBR from user space. Since it is VF61, you may consider as well moving SPI code to M4, where you may manipulate CTAR register as you wish.

Re: How to get spi-max-freqmax 66 MHz for dspi0 on MFV61NN151CMK50 processor.

Lyuda — Mon, 23 Jun 2025 10:35:01 GMT

kef2, Thank you for your reply!

I also came to the conclusion that the Linux driver does not support double data rate (DBR bit).

Thank you very much for your recommendations!!!