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SDHC layout recommendations

fernandoalcaide — Mon, 06 Jun 2016 11:49:36 GMT

Dear,

I am designing Board with Vybrid VF6 and I have doubt about SDHC layout recommentaions appears in paragraph 3.3.2.3 SD Card interface requirements of ref. doc. VYBRIDHDUG_HW_UserGuide.

In this paragrap appears:

1. The clock trace should be longer than the longest trace in the Data /Command group (+5mils).

Is 5mils minimun distance or maximum ?

2. SD card interface layout requirements are very similar to those for the DDR one (see Section 3.5,

“DDR routing rules”).

But in this section appears DDR3 recommnedations?

I need to kown routing recomentadion to SDHC.

Can somebody help me?

Thank you in advance.

Re: SDHC layout recommendations

timesyssupport — Wed, 08 Jun 2016 05:57:41 GMT

Hi Karina valencia Aguilar,

Can the NXP Vybrid Hardware team please comment on this?

Thanks

Timesys Support

Re: SDHC layout recommendations

karina_valencia — Wed, 08 Jun 2016 13:22:58 GMT

jiri-b36968 can you comment please?

Re: SDHC layout recommendations

jiri-b36968 — Thu, 09 Jun 2016 06:53:45 GMT

Hello Fernando,

yes, reference design uses DRAM memory type DDR3 (DDR is imprecise expression).

SDHC runs up to 50MHz.

- try to make lines short

- match all lines length.

- Add 5 mils to clk.

- try to keep lines on one layer.

- Ensure correct return path (continuous ground under lines)

- consider ESD protection if SD card is accessible to users.

/Jiri

Re: SDHC layout recommendations

fernandoalcaide — Thu, 09 Jun 2016 11:33:50 GMT

Thank you

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