topic Vybrid PLL3 PFD3 in Vybrid Processors

Vybrid PLL3 PFD3

ogj — Sat, 18 Apr 2020 18:10:39 GMT

I am trying to use PLL3 PFD3 clock as the source for the eSDHC1 clock. The problem is getting the PLL3 PFD3 functional. I am doing the following:

- Check ANADIG_PLL3_LOCK to verify that PLL3 is running and locked

- Enable PLL3 PFD3 by setting CCM_CCSR_PLL3_PFD3_EN high (see SDHC Clock Enable.png)

- Check that PDF3_CLKGATE bit in ANADIG_PLL3_PFD is low (which if I'm reading the RM correctly means that PLL3_PFD3 is enabled). Also the PLL3_PFD3 bit in CCM_CPPDSR is low meaning the output is enabled.

- However when I select PLL3_PFD3 as the clock source for ESDHC1 in CM_CSCMR1 (line in yellow), CCM_CCSR_PLL3_PFD3_EN goes low which means the PLL3 PFD3 is no longer functional. This is verified by SDHC1_PRSSTAT_SDSTB being low indicating no input clock.

What am I missing to get PLL3 PFD3 functional as the eSDHC1 clock?

Re: Vybrid PLL3 PFD3

ogj — Sat, 18 Apr 2020 18:37:17 GMT

After checking everything again, I have a few corrections:

- Check ANADIG_PLL3_LOCK to verify that PLL3 is running and locked

- Enable PLL3 PFD3 by setting CCM_CCSR_PLL3_PFD3_EN high (see SDHC Clock Enable.png)

- Check that PDF3_CLKGATE bit in ANADIG_PLL3_PFD is low (which if I'm reading the RM correctly means that PLL3_PFD3 is enabled)

- At this point I would expect PLL3 PFD3 to be functional. However when I check CCM_CPPDSR_PLL3_PFD3, it is high meaning that the output is disabled. Is there some additional gate that I can't find? How do I correctly turn on PLL3 PFD3?

Re: Vybrid PLL3 PFD3

jamesbone — Mon, 20 Apr 2020 22:28:32 GMT

Here is tthe candidate pseudo code for PLL initialization. Let me know if you finid anything.

I also added the code which check FXOSC status.

------------------------------------------------------------------------------------------------------------------------

/* Enable required clocks. Ungate by CCGRx */

CCM->CCGRx |= CCM_CCGRx_CGy(CLK_ON_ALL_MODES);

/* Enable external 32kHz clock */

SCSC->SOSC_CTR |= SCSC_SOSC_CTR_SOSC_EN_MASK;

/* Enable SIRC, PLL lock depends on it */

SCSC->SIRC_CTR |= SCSC_SIRC_CTR_SIRC_EN_MASK;

/*On-chip oscillator will not be powered down*/

CCM->CLPCR &= ~CCM_CLPCR_FXOSC_PWRDWN_MASK;

/*External high frequency oscillator will be enabled (ref_en_b = 0) - default, i.e., powered up */

CCM->CLPCR &= ~CCM_CLPCR_DIS_REF_OSC_MASK;

/*Enable FXOSC*/

CCM->CCR |= CCM_CCR_FXOSC_EN_MASK;

/*select 24 MHz XOSC clock, not 24MHz IRC clock*/

CCM->CCSR |= CCM_CCSR_FAST_CLK_SEL_MASK;

/* Enter RUN mode here - select PLL */

/* enable all the PLLs in Anadig */

/*PLL1 (System PLL) --> POWERDOWN=0, BYPASS=0, ENABLE=1, DIV_SELECT=1*/

ANADIG->PLL1_CTRL=0x00002001;

/*PLL2 (PLL 528) --> POWERDOWN=0, BYPASS=0, ENABLE=1, DIV_SELECT=1*/

ANADIG->PLL2_CTRL=0x00002001;

CCM->CCSR = (CCM_CCSR_PLL3_PFD4_EN_MASK | CCM_CCSR_PLL1_PFD_CLK_SEL(3) | \

0x0000FF00 | CCM_CCSR_FAST_CLK_SEL_MASK | (CCM_CCSR_SYS_CLK_SEL(4)));

CCM->CACRR=0x00000810; //ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2)

/*PLL2 (PLL 528) --> POWERDOWN=0, BYPASS=1, ENABLE=1, DIV_SELECT=1 (1->Fout=Fref*22, 0->Fout=Fref*22=>24M*22=528MHz) */

ANADIG->PLL2_CTRL=0x000 1 2001;

/* Disable PFD */

ANADIG->PLL2_PFD |= (PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE | PFD4_CLKGATE;

/*wait for LOCK of PLL2*/

While (!(ANADIG->PLL2_CTRL & ANADIG_PLL2_CTRL_LOCK));

/*After LOCK, PFD can be enabled. */

ANADIG->PLL2_PFD &= ~(PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE | PFD4_CLKGATE); // Enable PFD

CCM->CCSR = (CCM_CCSR_PLL3_PFD4_EN_MASK | CCM_CCSR_PLL1_PFD_CLK_SEL(3) | \

0x0000FF00 | CCM_CCSR_FAST_CLK_SEL_MASK | (CCM_CCSR_SYS_CLK_SEL(4)));

CCM->CACRR=0x00000810; //ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2)

The PFD must be disabled in the ANADIG register (ANADIG_PLLx_PFD).

The disable bit must be set (it is enabled by default after reset).