topic Re: ANADIG_PLL1_CTRL bit fields in Vybrid Processors

ANADIG_PLL1_CTRL bit fields

ealex — Wed, 18 Sep 2013 11:37:44 GMT

Hello

I have a question regarding the ANADIG_PLL1_CTRL register from the analog block.

In all reference manual versions (Vybrid Reference Manual, Rev. 6, 08/2013) ANADIG_PLL1_CTRL[DIV_SELECT] is bit 1, but setting that bit will not read back as 1, always as 0.

Instead, ANADIG_PLL1_CTRL[0] seems to be writable.

All other ANADIG_PLLn_CTRL registers seem to behave as described in the manual.

Is PLL1 limited to DIV_SELECT=0 ( X20 ? ) or is there an error in the manual and for PLL1 DIV_SELECT is bit 0 ?

Thanks,

Alexandru

Re: ANADIG_PLL1_CTRL bit fields

naoumgitnik — Wed, 18 Sep 2013 23:18:31 GMT

Hello Alexandru,

Before we proceed further, did you have a chance to review our software published on the Web and run on our boards to see how Vybrid does it? - It is for different OSs and quite well-commented.

Regards, Naoum Gitnik.

Re: ANADIG_PLL1_CTRL bit fields

ealex — Thu, 19 Sep 2013 08:08:52 GMT

Hello

I see that the same documentation problem applies to PLL2.

I'm using the chip bare-metal. I did not have a chance to look over the code published on the Web.

Re: ANADIG_PLL1_CTRL bit fields

karina_valencia — Thu, 19 Sep 2013 16:39:59 GMT

juangutierrez can you help on this case?

Re: Re: ANADIG_PLL1_CTRL bit fields

juangutierrez — Mon, 23 Sep 2013 17:36:00 GMT

From our software it seems the DIV_SELECT is bit0 not bit1 as the RM stated

================ SystemInit fxn @ /src/cpu/system_Vybrid.c ================

/* enable all the PLLs in Anadig */

ANADIG->PLL1_CTRL=0x00002001; //PLL1 (System PLL) --> POWERDOWN=0, BYPASS=0, ENABLE=1, DIV_SELECT=1 (1->Fout=Fref*22, 0->Fout=Fref*22=>24M*22=528MHz)

ANADIG->PLL2_CTRL=0x00002001; //PLL2 (PLL 528) --> POWERDOWN=0, BYPASS=0, ENABLE=1, DIV_SELECT=1 (1->Fout=Fref*22, 0->Fout=Fref*22=>24M*22=528MHz)

/* PLL3 --> 480 MHz PLL for USB0 - leave as default */

So it seems there is an error in RM and DIV_SELECT is indeed bit0 and bit1 is Reserved

Actually in imx6 the CCM_ANALOG_PLL_SYS has this distribution.

Re: ANADIG_PLL1_CTRL bit fields

ealex — Mon, 07 Oct 2013 14:40:46 GMT

Thanks guys.

I've got it working using BIT0.

Re: ANADIG_PLL1_CTRL bit fields

iankalinowski — Mon, 07 Oct 2013 18:35:06 GMT

Alexandru, where did you find Rev. 6 of the Vybrid Reference Manual? As far as I can tell on http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=018rH3E3E0, the latest revision available is Rev. 5 (07/2013).

Thanks,

Ian

Re: ANADIG_PLL1_CTRL bit fields

falstaff — Fri, 03 Oct 2014 09:23:18 GMT

The PLL1 DIV_SELECT is still wrong in the Rev. 7 manual, as well as PLL2 (as Alexandru stated).