Vybrid: Problem with DDR3 gate training

lukaszmajewski — Fri, 30 Nov 2018 11:39:41 GMT

Dear All,

This is a somewhat a follow up question for:

Vybrid: About DDR leveling feature on DDRMC. [1]

I've managed to run the RDLVL training (and receive results similar to expected one).

Unfortunately, I do not have access to DDRv tool.

I do use "non fly-by topology" - only single DDR3 x16 (512 MiB) memory is used.

The problem is with RDLVL_GTDL training.

When I do follow the "VFxxx Controller Reference Manual, Rev. 0, 10/2016", page 1597, 10.1.6.16.3.1
Software Gate Training in MC Evaluation Mode, point 3:

Add a 1⁄2 clock cycle increment to the DQS gate by setting PHY02[EN_HALF_CAS], PHY18[EN_HALF_CAS], PHY02[GATE_CFG] and PHY18[GATE_CFG] = 1.

GTDL: ---> RDLVL_GTDL_0
BITMAP [0x3f07f990]:
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Found delay: 64

(First bit is the response value when 0x0 is written to RDLVL_GTDL_DL_0, then the 0x1 is written and so on)

The found delay is 64 (0x40). Which according to [1] shall be regarded as 0 to be written to

CR106: RDLVL_GTDL_DL_0 (zero is the default value anyway).

Why this is true?

Unfortunately, after _any_ write to CR106 register (after first setting EN_HALF_CAS=GATE_CFG=1) the DDR3 seems to get misconfigured and the board hangs.

When I skip the before mentioned step 3 (adding 1/2 clock), I do receive:

GTDL: ======================
GTDL: PHY ungate to read DQS (GTDL)
GTDL: RDLVL_GTDL_DL_0_DFL: 0x0
GTDL: RDLVL_GTDL_DL_1_DFL: 0x0
GTDL: PHY_RDLVL_RES: 0x40
GTDL: PHY_RDLV_LOAD: 0x70
GTDL: PHY_RDLV_DLL: 0x30
GTDL: PHY_RDLV_EN: 0x30
GTDL: PHY_RDLV_RR: 0x40
GTDL: PHY_RDLV_RESP: 0x40
GTDL: PHY02_EN_HALF_CAS: 0x0
GTDL: PHY02_RD_DL_SET: 0x4
GTDL: PHY18_EN_HALF_CAS: 0x0
GTDL: PHY18_RD_DL_SET: 0x4
GTDL: SW_LVL_MODE: 0x3

GTDL: ---> RDLVL_GTDL_0
BITMAP [0x3f07f990]:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Found delay: 35

With this "training" the board doesn't hang (but I'm not sure if I want to use results from a wrong procedure).

Could somebody explain me why I may have an issue when following the guidelines from manual?

Maybe my DDRMC is wrongly setup and works by chance?

For example the PHY02 -> RD_DL_SET = 0x5 (not 0x4 recommended); WR_DB_ADJ = 0x1 (not 0x0 recommended).,

Also the CR126's => DDRMC_CR126_PHY_RDLAT(11) looks a bit too high (according to [1]).

The controller configuration values and procedure:

git.denx.de Git - u-boot.git/blob - board/phytec/pcm052/pcm052.c

git.denx.de Git - u-boot.git/blob - arch/arm/mach-imx/ddrmc-vf610.c

Best regards,

Łukasz

Re: Vybrid: Problem with DDR3 gate training

lukaszmajewski — Mon, 21 Jan 2019 07:47:43 GMT

Dear NXP community,

Could anyone provide any feedback on this question?

Thanks in advance,

Łukasz

topic Re: Vybrid: Problem with DDR3 gate training in Vybrid Processors

Vybrid: Problem with DDR3 gate training

Re: Vybrid: Problem with DDR3 gate training