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    <title>topic Vybrid : Setting core supply when executing SW RESET in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787767#M5914</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Dear Sir&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about the STEPs for the SW Reset.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I refer to the following community and AN4807 Rev.0, 10/2013.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/356894?q=Vybrid%20SW_RST"&gt;https://community.nxp.com/message/522684?q=Vybrid%20SW_RST&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Customers refer to AN 4807 Figure 6.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is described as the follows in the community.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;This switchover circuit is a make-before-break circuit with ~1ms of crossover time controlled by a single Vybrid GPIO which defaults to the Vybrid's internal LDO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SW Reset without Switching supplies beforehand: 0x00001201 (unexpected)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SW Reset after Switching to the Vybrid's LDO: 0x00040000 (expected)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;How should the core supply be set before issuing SW RESET?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(What is the Vybrid's LDO?)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(LDO with external ballast transistor? or internal LDO??)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is described as the follows in the AN4807 P16.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Low power stop mode sequence:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;1. Stop extensive part of the code.&lt;/P&gt;&lt;P&gt;2. Switch to power from external ballast transistor using GPIO pin.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;a) Open right FET transistor to start feeding from external ballast transistor.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;b) Close left FET transistor to stop supplying from 1.2 DC/DC converter.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;c) Disable DC/DC.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;3. LDO with external ballast transistor is used.&lt;/P&gt;&lt;P&gt;4. Jump in to low power stop mode.&lt;/P&gt;&lt;P&gt;5. Core is powered from internal LDO.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Executing STEP 2 a-c above, the core power supply will be changed to LDO with external ballast transistor.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If it is necessary to change the power supply to the internal LDO before executing the SW RESET, should we execute STEP 4?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Eishi SHIBUSAWA&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 12 Dec 2018 07:00:17 GMT</pubDate>
    <dc:creator>eishishibusawa</dc:creator>
    <dc:date>2018-12-12T07:00:17Z</dc:date>
    <item>
      <title>Vybrid : Setting core supply when executing SW RESET</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787767#M5914</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Dear Sir&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about the STEPs for the SW Reset.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I refer to the following community and AN4807 Rev.0, 10/2013.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/356894?q=Vybrid%20SW_RST"&gt;https://community.nxp.com/message/522684?q=Vybrid%20SW_RST&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Customers refer to AN 4807 Figure 6.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is described as the follows in the community.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;This switchover circuit is a make-before-break circuit with ~1ms of crossover time controlled by a single Vybrid GPIO which defaults to the Vybrid's internal LDO.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SW Reset without Switching supplies beforehand: 0x00001201 (unexpected)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SW Reset after Switching to the Vybrid's LDO: 0x00040000 (expected)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;How should the core supply be set before issuing SW RESET?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(What is the Vybrid's LDO?)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(LDO with external ballast transistor? or internal LDO??)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is described as the follows in the AN4807 P16.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Low power stop mode sequence:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;1. Stop extensive part of the code.&lt;/P&gt;&lt;P&gt;2. Switch to power from external ballast transistor using GPIO pin.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;a) Open right FET transistor to start feeding from external ballast transistor.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;b) Close left FET transistor to stop supplying from 1.2 DC/DC converter.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;c) Disable DC/DC.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;3. LDO with external ballast transistor is used.&lt;/P&gt;&lt;P&gt;4. Jump in to low power stop mode.&lt;/P&gt;&lt;P&gt;5. Core is powered from internal LDO.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Executing STEP 2 a-c above, the core power supply will be changed to LDO with external ballast transistor.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If it is necessary to change the power supply to the internal LDO before executing the SW RESET, should we execute STEP 4?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Eishi SHIBUSAWA&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Dec 2018 07:00:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787767#M5914</guid>
      <dc:creator>eishishibusawa</dc:creator>
      <dc:date>2018-12-12T07:00:17Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid : Setting core supply when executing SW RESET</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787768#M5915</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Dear NXP support member&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Please reply this question.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Best Regards,&lt;BR /&gt;Eishi SHIBUSAWA&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Dec 2018 00:13:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787768#M5915</guid>
      <dc:creator>eishishibusawa</dc:creator>
      <dc:date>2018-12-13T00:13:47Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid : Setting core supply when executing SW RESET</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787769#M5916</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;looks like you are trying to perform software reset, isn't it? You don't need any external circuitry for this. Almost every MCU&amp;nbsp;can be reset using&amp;nbsp;forgetting to feed or&amp;nbsp;forcing watchdog reset or any other means which may force MCU reset.&amp;nbsp;For&amp;nbsp;Vybrid&amp;nbsp;MCU SW reset please read about system reset controller and (18.3.2 SRC Control Register (SRC_SCR)). You need to set SW_RST bit.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Edward&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 04 Jan 2019 14:30:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Setting-core-supply-when-executing-SW-RESET/m-p/787769#M5916</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2019-01-04T14:30:20Z</dc:date>
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