Vybrid Processors中的主题 Re: UART framing errors do not get cleared

UART framing errors do not get cleared

pivkluka — Mon, 05 Dec 2016 12:50:59 GMT

We have a communication running over UART and we have issues with clearing framing errors.

If we communicate normally and do do not generate to many errors then we can clear S1[FE] flag without issues. ( we clear it by reading S1 and reading D ).

But we noticed that if we leave the UART running over longer times and produce lots of framing errors it becomes impossible to clear. S1 flag just wont reset any more after trying to clear it.

Did you observe anything similar?

Re: UART framing errors do not get cleared

pivkluka — Fri, 23 Dec 2016 13:02:05 GMT

Hi,

my setup includes

UART1 and 2 both operating in DMA mode

Here are some registry entries ->

RWFIFO & TWFIFO = 1

C3 = flags ORIE, FEIE and PEIE are set to 1

C2 = RE and TE are enabled. RIE and TIE are also enabled

C5 = TDMAS and RDMAS are set to 1

After some time running and creating lots of framing errors (thousands) it looks like S1[FE] does not get cleared again.

To clear S1[FE] I do this ->

Read register S1 and D.

Re: UART framing errors do not get cleared

jamesbone — Tue, 07 Feb 2017 17:05:13 GMT

Hello Pivk Luka,

Take in consideration that reading an empty data register to clear one of the flags of

the S1 register causes the FIFO pointers to become misaligned. A receive FIFO flush reinitializes the pointers.

A better way to prevent this situation is to always leave one byte in FIFO and this byte will be read eventually in

clearing the flag bit.

Re: UART framing errors do not get cleared

pivkluka — Wed, 15 Feb 2017 15:52:56 GMT

Hi,

Well as I told you I use DMA, and its not possible to really leave 1 byte there. And DMA by it self does not clear FE flag so to clear it I have to read that 1 byte. If there is any other way please let me know I will try it.

Re: UART framing errors do not get cleared

pivkluka — Tue, 10 Oct 2017 07:54:50 GMT

Any update on this?