<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Vybrid ProcessorsのトピックRe: Vybrid Core Identification &amp; Boot Issues</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629525#M5745</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Richard,&lt;/P&gt;&lt;P&gt;It's been confirmed that the parts I have are&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;MVF61NS152CMK50 (&lt;SPAN style="color: #0070c0;"&gt;A5-500, M4, L2 Cache, Security&lt;/SPAN&gt;), but the factory "tested and fused these parts to the part number marked on the device, MVF62NN152CMK40". I'm not exactly sure what this means with regard to what functionality I should expect though ...&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Nevertheless, to follow up on your RCON &amp;amp; booting suggestions - my RCON pins 1, 4-7, 16, 31 are all pulled low with 10k resistors.&lt;BR /&gt;The BOOT_CFG values I am able to read from SRC_SBMR1 confirm that these pins are read as low at system reset, so I can't see any reason why my boot configuration could be anything other than QuadSPI0.&lt;BR /&gt;Also the fact that I can attach via USB seems to indicate that it's not in the RCON31 endless loop state, but is in boot mode 0b01 - Serial Bootloader.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;It seems to me that the Vybrid is able to access the external QuadSPI flash, since the erase/program/verify operations all depend on the Vybrid being able to do so, and I have no trouble with this.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;So I'm still stumped as far as figuring out why some of these MVF61xx Vybrids boot and others don't while the older MVF50xx Vybrids all boot fine with the same QuadSPI image.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Interesting to note that even though one of the old MVF50xx boards doesn't have the 10k RCON pulldown resistors populated on 1 &amp;amp; 4-7, it still reads these pins as being low and boots fine (the 10k's on 16 &amp;amp; 31 are populated). This isn't a 'feature' I'm relying on though.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;I'm hoping to receive new samples soon of correctly marked &amp;amp; fused devices - not sure if they'll be MVF50xx or MVF61xx - but I'm still a little concerned that these new ones may not boot up for some as-yet unidentified reason...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;&amp;nbsp;- Bruce&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 30 Nov 2016 16:50:58 GMT</pubDate>
    <dc:creator>brucehansen</dc:creator>
    <dc:date>2016-11-30T16:50:58Z</dc:date>
    <item>
      <title>Vybrid Core Identification &amp; Boot Issues</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629522#M5742</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a custom board and firmware written and targeted for a MVF50NS151CMK50 Vybrid processor.&lt;/P&gt;&lt;P&gt;Although I am using a rudimentary RTOS, I am not using Linux or MQX (although I have ported some low-level driver code from MQX).&lt;/P&gt;&lt;P&gt;My code storage is a 4MB QuadSPI flash device, and I have 256MB or DDR3 SDRAM connected.&lt;/P&gt;&lt;P&gt;The Vybrid is configured to boot in mode 0b10 (RCON mode) and the relevant RCON pins are all pulled low to select QuadSPI0 as the boot device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My initial set of test boards were fitted with the MVF50xx and, as long as I respected the power supply / bootup issue addressed by PCN17176, my boards booted up and executed my firmware as expected.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Recently I received a new batch of boards - these ones were fitted with new Vybrid samples with mask revision 3N02G, intended to fix the PCN17176 issue.&lt;/P&gt;&lt;P&gt;We were notified in advance that the Vybrid samples we received would be a 'superset' of the version we intended to use - so instead of the MVF50NS152CMK50 (single A5 core, no L2 cache), we would get &lt;SPAN style="font-size: 11.0pt;"&gt;KVF61NS152CMK5 (dual A5/M4 cores, with L2 cache, A5 primary boot).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Since I never enable the M4 core or the L2 cache in my code, I didn't expect this to be any issue as the 'superset' devices should behave exactly like the ones we'd planned to use.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;However, after receiving the assembled boards I am now running into some issues &amp;amp; inconsistencies...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Immediately after assembly, the QuadSPI flash on all of the boards was programmed over JTAG (Segger J-Link connected to the Vybrid) and there were no issues - the programming succeeded and I can verify it.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;But of the 8 boards I have on hand to test, only one initially booted up - and this is where the strangeness begins.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;I noticed that the marking on the Vybrid IC packages wasn't what I expected. Instead of being&amp;nbsp;&lt;SPAN&gt;KVF61NS152CMK5, what I have is MVF62NN152CMK40 on all 8 boards&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;&lt;SPAN&gt;When refer to the Vybrid datasheet to decode this part number, I find that this part 'should' be a dual-core, but with the M4 as the primary boot core, and no L2 cache.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="font-size: 11.0pt;"&gt;So why did one of my boards boot when I've never written any M4 code for it?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;&lt;SPAN&gt;And the strangeness continues. While JTAG'ed to the board, I can access registers in the modules - and the MSCM in particular.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;These registers should tell me what type of cores I have in my device as well as what cache is present.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;For all 8 devices, it reports to me that I have an A5 with L2 cache as CP0 and an M4 as CP1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG style="font-size: 14.6667px;"&gt;But according to the datasheet &amp;amp; reference manual, for a MVF62xx device I should see the M4 as CP0 and the A5 with no L2 cache as CP1...&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;While experimenting with one of the boards - trying to get more useful information out of it, it also started to boot - and continues to do so. I don't know what I did to change it, but the firmware image is the same and I haven't blown any eFuses yet either.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;If I take one of my 'non-booting' boards, and attach to it over JTAG to try to debug running code (with my debug environment expecting to interact with the A5 core), I am able to pause the device and I see the PC register in the address range of the device's internal bootloader ROM. I can single-step through this code, but since I don't know what it's trying to do this doesn't tell me much.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;I also have access to the Vybrid's USB0 port, and if I take a 'non-booting' board and plug it into my PC, it enumerates as a 'HID-compliant vendor-defined device' and is recognized by the Vybrid MfgTool - which indicates to me that the ROM bootloader is in Serial Bootloader mode (mode 0b01) and not RCON boot mode (0b10) as it should be.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;But, when I check the SMBR1 &amp;amp; SMBR2 registers in the SRC module I see the values I expect to see for RCON-QuadSPI0 boot mode (&lt;SPAN style="font-size: 11.0pt;"&gt;SMBR1 0x00000000 &amp;amp;&amp;nbsp;SMBR2 0x02000001).&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;How do I figure out what I actually have? &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;Are these MVF62xx devices as marked - in which case why do any of them boot at all?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;Or are these mismarked MVF61xxx devices - in which case why does a working firmware image (tested on a MVF50xx) which is programmed the the QuadSPI flash &amp;amp; successfully verified not work?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;Why do some of these boards seem to boot to their internal ROM Serial bootloader (boot mode 0b01) instead of their configured RCON-QuadSPI0 mode?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Nov 2016 22:30:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629522#M5742</guid>
      <dc:creator>brucehansen</dc:creator>
      <dc:date>2016-11-28T22:30:17Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid Core Identification &amp; Boot Issues</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629523#M5743</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/richard_stulens"&gt;richard_stulens&lt;/A&gt;‌ will take this case.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Nov 2016 17:26:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629523#M5743</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-11-29T17:26:33Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid Core Identification &amp; Boot Issues</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629524#M5744</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Bruce,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me start with the&amp;nbsp;discrepancy between marking and fuses to clarify the situation for everyone else reading this thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;These samples that your received were not from a normal production run. They were tested an labeled outside the normal production flow for the purpose of general purpose samples. In this process, these parts&amp;nbsp;were incorrectly marked.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Going by the fuse and SMBR info&amp;nbsp;you sent per e-mail, the parts you received are Dual core A5 primary with Speed grade 500 MHz and thus will be able to execute your A5 code. This explains why 2 boards did boot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The reason for the non-booting parts to be in serial boot mode is quite likely because Serial Boot mode is the fall-back boot mode when the boot from the specified device (QSPI in your case) fails.&lt;/P&gt;&lt;P&gt;You mentioned that the&amp;nbsp;2 booting boards were initially not booting and started to boot later&amp;nbsp;for no apparent reason. This triggers a thought that some of the&amp;nbsp;RCON pins may be floating. Floating pins may alter the boot configuration causing the boot to fail, even though RCON[7:0] selects QSPI. Ex.&amp;nbsp; if RCON[31] is set it will send the boot in an endless loop.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this covers all your questions and allows for getting the other boards to boot as well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Richard&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Nov 2016 13:01:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629524#M5744</guid>
      <dc:creator>richard_stulens</dc:creator>
      <dc:date>2016-11-30T13:01:40Z</dc:date>
    </item>
    <item>
      <title>Re: Vybrid Core Identification &amp; Boot Issues</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629525#M5745</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Richard,&lt;/P&gt;&lt;P&gt;It's been confirmed that the parts I have are&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;MVF61NS152CMK50 (&lt;SPAN style="color: #0070c0;"&gt;A5-500, M4, L2 Cache, Security&lt;/SPAN&gt;), but the factory "tested and fused these parts to the part number marked on the device, MVF62NN152CMK40". I'm not exactly sure what this means with regard to what functionality I should expect though ...&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Nevertheless, to follow up on your RCON &amp;amp; booting suggestions - my RCON pins 1, 4-7, 16, 31 are all pulled low with 10k resistors.&lt;BR /&gt;The BOOT_CFG values I am able to read from SRC_SBMR1 confirm that these pins are read as low at system reset, so I can't see any reason why my boot configuration could be anything other than QuadSPI0.&lt;BR /&gt;Also the fact that I can attach via USB seems to indicate that it's not in the RCON31 endless loop state, but is in boot mode 0b01 - Serial Bootloader.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;It seems to me that the Vybrid is able to access the external QuadSPI flash, since the erase/program/verify operations all depend on the Vybrid being able to do so, and I have no trouble with this.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;So I'm still stumped as far as figuring out why some of these MVF61xx Vybrids boot and others don't while the older MVF50xx Vybrids all boot fine with the same QuadSPI image.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Interesting to note that even though one of the old MVF50xx boards doesn't have the 10k RCON pulldown resistors populated on 1 &amp;amp; 4-7, it still reads these pins as being low and boots fine (the 10k's on 16 &amp;amp; 31 are populated). This isn't a 'feature' I'm relying on though.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;I'm hoping to receive new samples soon of correctly marked &amp;amp; fused devices - not sure if they'll be MVF50xx or MVF61xx - but I'm still a little concerned that these new ones may not boot up for some as-yet unidentified reason...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;&amp;nbsp;- Bruce&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Nov 2016 16:50:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/629525#M5745</guid>
      <dc:creator>brucehansen</dc:creator>
      <dc:date>2016-11-30T16:50:58Z</dc:date>
    </item>
    <item>
      <title>This an automatic process.  We are marking this post as s...</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/1139679#M6165</link>
      <description>&lt;B&gt;This an automatic process.&lt;/B&gt;&lt;BR /&gt;&lt;BR /&gt;
We are marking this post as solved, due to the either low activity or any reply marked as correct.&lt;BR /&gt;&lt;BR /&gt;
If you have additional questions, please create a new post and reference to this closed post.&lt;BR /&gt;&lt;BR /&gt;
NXP Community!</description>
      <pubDate>Thu, 03 Sep 2020 20:20:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Vybrid-Core-Identification-Boot-Issues/m-p/1139679#M6165</guid>
      <dc:creator>CommunityBot</dc:creator>
      <dc:date>2020-09-03T20:20:35Z</dc:date>
    </item>
  </channel>
</rss>

