topic SPI - set inactive state of SOUT in Vybrid Processors https://community.nxp.com/t5/Vybrid-Processors/SPI-set-inactive-state-of-SOUT/m-p/628396#M5740 <HTML><HEAD></HEAD><BODY><P>SPI on Vybrid can be configured through a dedicated set of registers.</P><P>Inactive state for PCS and SCK can be configured with PCSIS (in SPIx_MCR) and CPOL (in SPIx_CTARn).</P><P>I don't find a way to set the inactive state for SOUT, and with an oscilloscope I see that this is HIGH.</P><P>Is there a way to set it to LOW?</P></BODY></HTML> Tue, 07 Mar 2017 08:14:11 GMT vix 2017-03-07T08:14:11Z SPI - set inactive state of SOUT https://community.nxp.com/t5/Vybrid-Processors/SPI-set-inactive-state-of-SOUT/m-p/628396#M5740 <HTML><HEAD></HEAD><BODY><P>SPI on Vybrid can be configured through a dedicated set of registers.</P><P>Inactive state for PCS and SCK can be configured with PCSIS (in SPIx_MCR) and CPOL (in SPIx_CTARn).</P><P>I don't find a way to set the inactive state for SOUT, and with an oscilloscope I see that this is HIGH.</P><P>Is there a way to set it to LOW?</P></BODY></HTML> Tue, 07 Mar 2017 08:14:11 GMT https://community.nxp.com/t5/Vybrid-Processors/SPI-set-inactive-state-of-SOUT/m-p/628396#M5740 vix 2017-03-07T08:14:11Z Re: SPI - set inactive state of SOUT https://community.nxp.com/t5/Vybrid-Processors/SPI-set-inactive-state-of-SOUT/m-p/628397#M5741 <HTML><HEAD></HEAD><BODY><P>There is no way of configuring the inactive state of the SOUT signal, it is always High.</P><P><BR />Have a great day,<BR />Artur</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Mon, 27 Mar 2017 09:16:17 GMT https://community.nxp.com/t5/Vybrid-Processors/SPI-set-inactive-state-of-SOUT/m-p/628397#M5741 art 2017-03-27T09:16:17Z