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    <title>topic Re: DMAMUX_CHCFG Source for SPI0 transmit/receive in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223242#M57</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/timesyssupport"&gt;timesyssupport&lt;/A&gt; can you help with this case?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 12 Feb 2014 17:55:11 GMT</pubDate>
    <dc:creator>karina_valencia</dc:creator>
    <dc:date>2014-02-12T17:55:11Z</dc:date>
    <item>
      <title>DMAMUX_CHCFG Source for SPI0 transmit/receive</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223241#M56</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to establish a slave SPI0 interface with DMA0 with DMAMUX2. When I write the DMAMUX_CHCFG_SOURCE(13) to the DMAMUX0_CHCFG2 I get all &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DOE,&lt;/P&gt;&lt;P&gt;DAE,&lt;/P&gt;&lt;P&gt;SOE,&lt;/P&gt;&lt;P&gt;SAE &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;error bits of DMA0 Error status registere are set.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;DMAMUX0_CHCFG2 = DMAMUX_CHCFG_SOURCE(13) |&amp;nbsp; DMAMUX_CHCFG_ENBL_MASK;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using the number 13 because of table 8-2 of ref. manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How can I tell the DMAMUX unit that I will connect it SPI0 transmit/receive? &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks and best regards&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mehmet Ali Ipin&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Feb 2014 09:40:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223241#M56</guid>
      <dc:creator>MehmetAliIpin</dc:creator>
      <dc:date>2014-02-11T09:40:37Z</dc:date>
    </item>
    <item>
      <title>Re: DMAMUX_CHCFG Source for SPI0 transmit/receive</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223242#M57</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/timesyssupport"&gt;timesyssupport&lt;/A&gt; can you help with this case?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Feb 2014 17:55:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223242#M57</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2014-02-12T17:55:11Z</dc:date>
    </item>
    <item>
      <title>Re: DMAMUX_CHCFG Source for SPI0 transmit/receive</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223243#M58</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Mehmet,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have you followed both notes in section 22.3.1 in the Vybrid reference manual? I am unsure if your code:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;BR /&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;DMAMUX0_CHCFG2 = DMAMUX_CHCFG_SOURCE(13) |&amp;nbsp; DMAMUX_CHCFG_ENBL_MASK;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;BR /&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt; &lt;/STRONG&gt;will work due to the note, "Before changing the trigger or source settings, a DMA channel must be disabled via the CHCFGn[ENBL] bit.". Try disabling the CHCFGn[ENBL] bit, set the source, then enable the CHCFGn[ENBL] bit.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Feb 2014 21:00:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223243#M58</guid>
      <dc:creator>timesyssupport</dc:creator>
      <dc:date>2014-02-12T21:00:15Z</dc:date>
    </item>
    <item>
      <title>Re: DMAMUX_CHCFG Source for SPI0 transmit/receive</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223244#M59</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Timesys support,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you very much,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now I can transmit with SPI0 DMA channel.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Feb 2014 06:46:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/DMAMUX-CHCFG-Source-for-SPI0-transmit-receive/m-p/223244#M59</guid>
      <dc:creator>MehmetAliIpin</dc:creator>
      <dc:date>2014-02-13T06:46:56Z</dc:date>
    </item>
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