topic Re: Vybrid Cortex-A5 cache access latency in Vybrid Processors

Vybrid Cortex-A5 cache access latency

hjk — Mon, 13 Jun 2016 12:38:34 GMT

On "Understand Vybrid Architecture" cache access latency

Processor registers 1 cycle

On-chip L1 cache 1-2 cycles

On-chip L2 cache 8 cycles

Main memory, L3, dynamic RAM 30-100 cycles

Back-up memory, hard disk, L4 > 500 cycles

But I used DS-5 to measure cache access latency

I got

L1 cache read hit 32 cycle, write hit 3 cycle

when LDR follows STR it becomes 71 cycle on hit

How does that happen?

Are there more accurate numbers of cache access latency for vybrid VF6xx processor?

I found that data caching was disabled by default, beside SCTLR.C what should I set to enable it?

Re: Vybrid Cortex-A5 cache access latency

karina_valencia — Mon, 13 Jun 2016 21:55:09 GMT

timesyssupport can you help to review this case?

Re: Vybrid Cortex-A5 cache access latency

timesyssupport — Fri, 17 Jun 2016 14:05:04 GMT

Hi,

I found some cache-related settings at mqx/source/psp/cortex_a/

vybrid.h, lines 73-109 (this is for running MQX on either the A5 or M4 core). Regarding dcache in coretx-a5, read the "MQX_User_Guide.pdf" document and refer the cache_a5.c (MQX_4_1_1_LINUX_GA/mqx/source/psp/cortex_a/cache_a5.c) file.

To enable/access the data cache, we should have to enable MMC, which is discussed in below thread:
https://community.nxp.com/thread/315672

Thanks,
Timesys Support

This an automatic process. We are marking this post as s...

CommunityBot — Thu, 03 Sep 2020 19:12:36 GMT

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