topic Re: Configuring CKO1 output PLL5 in Vybrid Processors

Configuring CKO1 output PLL5

Nouchi — Tue, 29 Mar 2016 12:27:58 GMT

Hello,

I started with Yocto Jethro, and I successfully built a system image with the new 4.1 kernel.

I customized it with device tree, but I'm stuck with network. Our design use LAN8720 like Auto EVB, but RMII clock is provided by CKO1 output, CKO1(PTB10) is connected to RMII_CLKIN (PTA6) and connected to LAN8720 CLKIN (see this). This design needs few BSP customizations and it worked fine with the old 3.0.15 kernel from Timesys.

PTB10 is well configured as CKO1 mode by device tree, and CCSOR, PLL5_CTRL configured by u-boot.

At the end of kernel init, just before rfs mount, RMII CLK stops, then eth0 becomes unavailable.

But I don't know if PTB10 iomux mode changed or CCSOR/PLL5_CTRL.

Any suggestions?

Regards

Emmanuel

Re: Configuring CKO1 output PLL5

karina_valencia — Fri, 01 Apr 2016 21:04:02 GMT

timesyssupport can you help to attend this case?

Re: Configuring CKO1 output PLL5

timesyssupport — Mon, 04 Apr 2016 22:25:01 GMT

Hi Emmanuel,

We recently worked with this on different Vybrid hardware with the 4.1 kernel. I have attached several patches - one to setup CKO1 with ENET_CLK (you will need to add the 'enet-ref-clock-cko1' property to your device tree or remove this check in the patch), and another that cleans up pinmux settings for the LAN8720 PHY. Let me know if this helps.

Thanks,

Timesys Support