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    <title>topic Re: Not all data sent out SPI using DMA in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/Not-all-data-sent-out-SPI-using-DMA/m-p/507213#M5437</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I now have this functioning as I would expect.&amp;nbsp; The major changes I made were to change the DMAMux channel to be a modulus of the DMA channel (not sure if this is needed) and switching the data send counts between the minor and major loops.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;INIT FUNCTION&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;#define SIZE8&amp;nbsp; 0&lt;/P&gt;&lt;P&gt;#define SIZE16 1&lt;/P&gt;&lt;P&gt;#define SIZE32 2&lt;/P&gt;&lt;P&gt;#define SIZE64 3&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//Test using DMA 0 Channel 20, MUX 1 (SPI2)&lt;/P&gt;&lt;P&gt;CCM_CCGR0 |= CCM_CCGR0_CG5(3); //DMA Channel Mux1&lt;/P&gt;&lt;P&gt;CCM_CCPGR1 |= CCM_CCPGR1_PPCG8(3) | CCM_CCPGR1_PPCG9(3); //DMA0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;_int_install_kernel_isr(NVIC_DSPI2, SPI2_ISR);&lt;/P&gt;&lt;P&gt;_bsp_int_init(NVIC_DSPI2, 3, 0, TRUE);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI2_RSER |= 0x03000000; //Enable DMA request for TFFF (transmit buffer fill flash)&lt;/P&gt;&lt;P&gt;SPI2_CTAR0 &amp;amp;= 0xFFFF0000;&lt;/P&gt;&lt;P&gt;SPI2_MCR = 0x803F1002;&lt;/P&gt;&lt;P&gt;SPI2_TCR = 0;&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 = 0; //Clear source&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SADDR = 0; //Source Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_ATTR = DMA_ATTR_SMOD(0) | DMA_ATTR_SSIZE(SIZE8) //Modulo and access size for source&lt;/P&gt;&lt;P&gt;&amp;nbsp; | DMA_ATTR_DMOD(0) | DMA_ATTR_DSIZE(SIZE8);//and destination&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SOFF = 1; //source address offset in bytes after each access&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SLAST = 0; //source address adjustment on major loop completion - used to reset TCD&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DADDR = (volatile void*)(&amp;amp;SPI2_PUSHR); //Destination Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CITER_ELINKNO = 1; //current major count&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DOFF = 0; //destination address offset in bytes after each access&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DLASTSGA = 0; //destination address adjustment on major loop completion - used to reset TCD&lt;/P&gt;&lt;P&gt;DMA0_TCD20_BITER_ELINKNO = 1; //total major iteration count&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;TRANSMIT FUNCTION&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;//Setup the structure (data pointer and data size)&lt;/P&gt;&lt;P&gt;rw.BUFFER_LENGTH = writeData-&amp;gt;dataSize;&lt;/P&gt;&lt;P&gt;rw.WRITE_BUFFER = (char_ptr)writeData-&amp;gt;data;&lt;/P&gt;&lt;P&gt;rw.READ_BUFFER = NULL;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;minorLoopSize = 1;&lt;/P&gt;&lt;P&gt;majorLoopSize = rw.BUFFER_LENGTH / minorLoopSize;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 = 0; //Source = Clear&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SADDR = (uint32_t)(rw.WRITE_BUFFER); //Source Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_NBYTES_MLNO = DMA_NBYTES_MLNO_NBYTES(minorLoopSize); //total number of bytes in minor loop&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CITER_ELINKNO = majorLoopSize; //current major count&lt;/P&gt;&lt;P&gt;DMA0_TCD20_BITER_ELINKNO = majorLoopSize; //total major iteration count&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 = DMAMUX_CHCFG_SOURCE(11); //Source = SPI.2.TX&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 |= DMAMUX_CHCFG_ENBL_MASK;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CSR = 0x08; //set all bits to zero&lt;/P&gt;&lt;P&gt;DMA0_SERQ = 20;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CSR |= 1;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 12 May 2016 16:19:59 GMT</pubDate>
    <dc:creator>DanKSI</dc:creator>
    <dc:date>2016-05-12T16:19:59Z</dc:date>
    <item>
      <title>Not all data sent out SPI using DMA</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Not-all-data-sent-out-SPI-using-DMA/m-p/507212#M5436</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using an Emcraft Vybrid SOM and am trying to transmit SPI data using DMA.&amp;nbsp; This is occurring on the M4 and I have the SPI configured using MQX, but use the following source for the actual transmit.&amp;nbsp; What I see on the SPI signals is that some of the data is sent, but not all of it, but it is the same data everytime.&amp;nbsp; I am sending a 48 byte buffer of incrementing values (0, 1, 2, 3, 4, 5, etc.).&amp;nbsp; What I am seeing makes me think that the DMA is sending data to the SPI transmit register as fast as it can, and is not being throttled by the SPI TFFF DMA request.&amp;nbsp; I am viewing the transmit data on a logic analyzer.&amp;nbsp; The SPI TCR is of size 13, and the TXFR FIFO registers show the data that was actually transmitted.&amp;nbsp; I am not using the receive of the SPI.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;INIT FUNCTION&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;#define SIZE8&amp;nbsp; 0&lt;/P&gt;&lt;P&gt;#define SIZE16 1&lt;/P&gt;&lt;P&gt;#define SIZE32 2&lt;/P&gt;&lt;P&gt;#define SIZE64 3&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//Test using DMA 0 Channel 20, MUX 1&lt;/P&gt;&lt;P&gt;CCM_CCGR0 |= CCM_CCGR0_CG5(3); //DMA Channel Mux1&lt;/P&gt;&lt;P&gt;CCM_CCPGR1 |= CCM_CCPGR1_PPCG8(3) | CCM_CCPGR1_PPCG9(3); //DMA0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;_int_install_kernel_isr(NVIC_DSPI2, SPI2_ISR);&lt;/P&gt;&lt;P&gt;_bsp_int_init(NVIC_DSPI2, 3, 0, TRUE);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI2_RSER |= 0x03000000; //Enable DMA request for TFFF (transmit buffer fill flash)&lt;/P&gt;&lt;P&gt;SPI2_MCR = 0x803F1002;&lt;/P&gt;&lt;P&gt;SPI2_TCR = 0;&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG9 = 0; //Clear source&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SADDR = 0; //Source Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_ATTR = DMA_ATTR_SMOD(0) | DMA_ATTR_SSIZE(SIZE8) //Modulo and access size for source&lt;/P&gt;&lt;P&gt;&amp;nbsp; | DMA_ATTR_DMOD(0) | DMA_ATTR_DSIZE(SIZE8);//and destination&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SOFF = 1; //source address offset in bytes after each access&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SLAST = 0; //source address adjustment on major loop completion - used to reset TCD&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DADDR = (volatile void*)(&amp;amp;SPI2_PUSHR); //Destination Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CITER_ELINKNO = 1; //current major count&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DOFF = 0; //destination address offset in bytes after each access&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DLASTSGA = 0; //destination address adjustment on major loop completion - used to reset TCD&lt;/P&gt;&lt;P&gt;DMA0_TCD20_BITER_ELINKNO = 1; //total major iteration count&lt;/P&gt;&lt;P&gt;DMA0_SERQ = 20;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;TRANSMIT FUNCTION&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;//Setup the structure (data pointer and data size)&lt;/P&gt;&lt;P&gt;rw.BUFFER_LENGTH = writeData-&amp;gt;dataSize;&lt;/P&gt;&lt;P&gt;rw.WRITE_BUFFER = (char_ptr)writeData-&amp;gt;data;&lt;/P&gt;&lt;P&gt;rw.READ_BUFFER = NULL;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;_DCACHE_FLUSH(); //Cleans up data in external memory&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG9 = 0; //Source = Clear&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SADDR = (uint32_t)(rw.WRITE_BUFFER); //Source Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_NBYTES_MLNO = DMA_NBYTES_MLNO_NBYTES(rw.BUFFER_LENGTH); //total number of bytes in minor loop&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG9 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(11); //Source = SPI.2.TX&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CSR = 0x08; //set all bits to zero&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CSR |= 1;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;RESULTS&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;0x00, 0x01, 0x02, 0x03, 0x04, 0x07, 0x0C, 0x12, 0x18, 0x1E, 0x24, 0x29, 0x2F&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for any help,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Dan K.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 May 2016 13:54:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Not-all-data-sent-out-SPI-using-DMA/m-p/507212#M5436</guid>
      <dc:creator>DanKSI</dc:creator>
      <dc:date>2016-05-06T13:54:19Z</dc:date>
    </item>
    <item>
      <title>Re: Not all data sent out SPI using DMA</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/Not-all-data-sent-out-SPI-using-DMA/m-p/507213#M5437</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I now have this functioning as I would expect.&amp;nbsp; The major changes I made were to change the DMAMux channel to be a modulus of the DMA channel (not sure if this is needed) and switching the data send counts between the minor and major loops.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;INIT FUNCTION&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;#define SIZE8&amp;nbsp; 0&lt;/P&gt;&lt;P&gt;#define SIZE16 1&lt;/P&gt;&lt;P&gt;#define SIZE32 2&lt;/P&gt;&lt;P&gt;#define SIZE64 3&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//Test using DMA 0 Channel 20, MUX 1 (SPI2)&lt;/P&gt;&lt;P&gt;CCM_CCGR0 |= CCM_CCGR0_CG5(3); //DMA Channel Mux1&lt;/P&gt;&lt;P&gt;CCM_CCPGR1 |= CCM_CCPGR1_PPCG8(3) | CCM_CCPGR1_PPCG9(3); //DMA0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;_int_install_kernel_isr(NVIC_DSPI2, SPI2_ISR);&lt;/P&gt;&lt;P&gt;_bsp_int_init(NVIC_DSPI2, 3, 0, TRUE);&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI2_RSER |= 0x03000000; //Enable DMA request for TFFF (transmit buffer fill flash)&lt;/P&gt;&lt;P&gt;SPI2_CTAR0 &amp;amp;= 0xFFFF0000;&lt;/P&gt;&lt;P&gt;SPI2_MCR = 0x803F1002;&lt;/P&gt;&lt;P&gt;SPI2_TCR = 0;&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 = 0; //Clear source&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SADDR = 0; //Source Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_ATTR = DMA_ATTR_SMOD(0) | DMA_ATTR_SSIZE(SIZE8) //Modulo and access size for source&lt;/P&gt;&lt;P&gt;&amp;nbsp; | DMA_ATTR_DMOD(0) | DMA_ATTR_DSIZE(SIZE8);//and destination&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SOFF = 1; //source address offset in bytes after each access&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SLAST = 0; //source address adjustment on major loop completion - used to reset TCD&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DADDR = (volatile void*)(&amp;amp;SPI2_PUSHR); //Destination Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CITER_ELINKNO = 1; //current major count&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DOFF = 0; //destination address offset in bytes after each access&lt;/P&gt;&lt;P&gt;DMA0_TCD20_DLASTSGA = 0; //destination address adjustment on major loop completion - used to reset TCD&lt;/P&gt;&lt;P&gt;DMA0_TCD20_BITER_ELINKNO = 1; //total major iteration count&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;TRANSMIT FUNCTION&lt;/P&gt;&lt;P&gt;---------------------------------&lt;/P&gt;&lt;P&gt;//Setup the structure (data pointer and data size)&lt;/P&gt;&lt;P&gt;rw.BUFFER_LENGTH = writeData-&amp;gt;dataSize;&lt;/P&gt;&lt;P&gt;rw.WRITE_BUFFER = (char_ptr)writeData-&amp;gt;data;&lt;/P&gt;&lt;P&gt;rw.READ_BUFFER = NULL;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;minorLoopSize = 1;&lt;/P&gt;&lt;P&gt;majorLoopSize = rw.BUFFER_LENGTH / minorLoopSize;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 = 0; //Source = Clear&lt;/P&gt;&lt;P&gt;DMA0_TCD20_SADDR = (uint32_t)(rw.WRITE_BUFFER); //Source Address For Transfer&lt;/P&gt;&lt;P&gt;DMA0_TCD20_NBYTES_MLNO = DMA_NBYTES_MLNO_NBYTES(minorLoopSize); //total number of bytes in minor loop&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CITER_ELINKNO = majorLoopSize; //current major count&lt;/P&gt;&lt;P&gt;DMA0_TCD20_BITER_ELINKNO = majorLoopSize; //total major iteration count&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 = DMAMUX_CHCFG_SOURCE(11); //Source = SPI.2.TX&lt;/P&gt;&lt;P&gt;DMAMUX1_CHCFG4 |= DMAMUX_CHCFG_ENBL_MASK;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CSR = 0x08; //set all bits to zero&lt;/P&gt;&lt;P&gt;DMA0_SERQ = 20;&lt;/P&gt;&lt;P&gt;DMA0_TCD20_CSR |= 1;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 May 2016 16:19:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/Not-all-data-sent-out-SPI-using-DMA/m-p/507213#M5437</guid>
      <dc:creator>DanKSI</dc:creator>
      <dc:date>2016-05-12T16:19:59Z</dc:date>
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