<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic RTIC in Vybrid Processors</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477763#M5200</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am working on Vybrid platform to enable RTIC feature. When I wrote those registers, the value I read back was always zero. Even I used U-boot. For example:&lt;/P&gt;&lt;P&gt;I wrote : CAAM_RTIC_BASE_PTR-&amp;gt;RWDOG = 0xffff;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CAAM_RTIC_BASE_PTR-&amp;gt;RTHR = 0x1;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then the value I read back was :&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CAAM_RTIC_BASE_PTR-&amp;gt;RWDOG = 0x0;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CAAM_RTIC_BASE_PTR-&amp;gt;RTHR = 0x0;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Somebody can tell me why?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 15 Mar 2016 14:44:50 GMT</pubDate>
    <dc:creator>东升王</dc:creator>
    <dc:date>2016-03-15T14:44:50Z</dc:date>
    <item>
      <title>RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477763#M5200</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am working on Vybrid platform to enable RTIC feature. When I wrote those registers, the value I read back was always zero. Even I used U-boot. For example:&lt;/P&gt;&lt;P&gt;I wrote : CAAM_RTIC_BASE_PTR-&amp;gt;RWDOG = 0xffff;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CAAM_RTIC_BASE_PTR-&amp;gt;RTHR = 0x1;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then the value I read back was :&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CAAM_RTIC_BASE_PTR-&amp;gt;RWDOG = 0x0;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CAAM_RTIC_BASE_PTR-&amp;gt;RTHR = 0x0;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Somebody can tell me why?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Mar 2016 14:44:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477763#M5200</guid>
      <dc:creator>东升王</dc:creator>
      <dc:date>2016-03-15T14:44:50Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477764#M5201</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/timesyssupport"&gt;timesyssupport&lt;/A&gt;​ can you help to review this case?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Mar 2016 21:46:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477764#M5201</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-03-17T21:46:10Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477765#M5202</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Dongsheng,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ensure that, RTIC is not in Run-time mode before writing to those registers as they are read only while in Run-time mode. Use RSTA register to find out the state of RTIC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 21 Mar 2016 12:30:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477765#M5202</guid>
      <dc:creator>timesyssupport</dc:creator>
      <dc:date>2016-03-21T12:30:54Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477766#M5203</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, before I wrote these registers. I checked RSTA register. It is always zero. Actually every registers are always zero. Even I read and wrote them with U-boot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 22 Mar 2016 03:24:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477766#M5203</guid>
      <dc:creator>东升王</dc:creator>
      <dc:date>2016-03-22T03:24:31Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477767#M5204</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; RTIC registers are set with 0 by default.I referred VYBRIDSRM and don't have much information to share. &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/karinavalencia"&gt;karinavalencia&lt;/A&gt; Can you ask the NXP Vybrid team to comment with any other information?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Timesys Support&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Mar 2016 11:53:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477767#M5204</guid>
      <dc:creator>timesyssupport</dc:creator>
      <dc:date>2016-03-23T11:53:07Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477768#M5205</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/rendy"&gt;rendy&lt;/A&gt;​ can you share your comments?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Mar 2016 15:44:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477768#M5205</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-03-23T15:44:10Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477769#M5206</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sure, no problem!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Mar 2016 17:10:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477769#M5206</guid>
      <dc:creator>东升王</dc:creator>
      <dc:date>2016-03-23T17:10:42Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477770#M5207</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/rendy"&gt;rendy&lt;/A&gt;​ do you have an update?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 01 Apr 2016 21:06:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477770#M5207</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-04-01T21:06:05Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477771#M5208</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please send me a short example which demonstrates this and I will check it soon. You can use TWR-VF65GS10 sample code.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Rene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Apr 2016 12:04:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477771#M5208</guid>
      <dc:creator>rendy</dc:creator>
      <dc:date>2016-04-14T12:04:29Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477772#M5209</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/dongshengwang"&gt;dongshengwang&lt;/A&gt;​ did you get previous comment?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Apr 2016 16:00:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477772#M5209</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-04-18T16:00:12Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477773#M5210</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Karinavalencia&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Sorry I just got your email.  Here is my code for rtic. Thanks for your &lt;/P&gt;&lt;P&gt;help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Dongsheng Wang&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Apr 2016 16:38:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477773#M5210</guid>
      <dc:creator>东升王</dc:creator>
      <dc:date>2016-04-18T16:38:37Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477774#M5211</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/rendy"&gt;rendy&lt;/A&gt;​ FYI&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 18 Apr 2016 16:44:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477774#M5211</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-04-18T16:44:32Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477775#M5212</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please send me *working* example - send me the project with all headers and sources needed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;BR /&gt;Rene&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Apr 2016 12:45:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477775#M5212</guid>
      <dc:creator>rendy</dc:creator>
      <dc:date>2016-04-26T12:45:32Z</dc:date>
    </item>
    <item>
      <title>Re: RTIC</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477776#M5213</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/东升王"&gt;东升王&lt;/A&gt;​&amp;nbsp; did you send Rene&amp;nbsp; the information requested?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 02 May 2016 18:14:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/477776#M5213</guid>
      <dc:creator>karina_valencia</dc:creator>
      <dc:date>2016-05-02T18:14:24Z</dc:date>
    </item>
    <item>
      <title>This an automatic process.  We are marking this post as s...</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/1138343#M6135</link>
      <description>&lt;B&gt;This an automatic process.&lt;/B&gt;&lt;BR /&gt;&lt;BR /&gt;
We are marking this post as solved, due to the either low activity or any reply marked as correct.&lt;BR /&gt;&lt;BR /&gt;
If you have additional questions, please create a new post and reference to this closed post.&lt;BR /&gt;&lt;BR /&gt;
NXP Community!</description>
      <pubDate>Thu, 03 Sep 2020 18:37:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/RTIC/m-p/1138343#M6135</guid>
      <dc:creator>CommunityBot</dc:creator>
      <dc:date>2020-09-03T18:37:01Z</dc:date>
    </item>
  </channel>
</rss>

