DDRMC_PHY02 Register Reserved Bits?

rmcginnis — Wed, 15 Jan 2014 17:17:20 GMT

The file ddr.c included with the Freescale tower example source code sets 0x01210080 in the PHY02,18,&34 registers. When looking at the Vybrid reference manual (Rev 5, 07/2013) bits 7, 16 and 24 are set within the Reserved areas of the PHY Register 2 is set. When I write 0xFFFFFFFF to that register I'm able to read back 0xFFFFFFFF which doesn't agree with the reference manual documentation.

What are the reserved register bits that are set within the PHY02 register? Is the reference manual documentation correct?

ddr.c - source code

#define PHY_CTRL

0x01210080

// phy_gate_lpbk_ctrl_reg freq set 0

reg32_write(DDR_PHY002, PHY_CTRL); // read delay bit21:19

reg32_write(DDR_PHY018, PHY_CTRL); // phase_detect_sel bit18:16

reg32_write(DDR_PHY034, PHY_CTRL); // bit lpbk_ctrl bit12

Re: DDRMC_PHY02 Register Reserved Bits?

naoumgitnik — Thu, 16 Jan 2014 21:20:22 GMT

Dear rmcginnis,

Bits like the ones mentioned, i.e. those whose values are changed by our code but described as "Reserved" in the documentation, are "For Internal Use Only". In this case, customers are supposed to use our values, the bits' functions being considered confidential.
Another type of bits, whose values are "Don't Care", are simply not used; it usually happens when a block is designed for more than one chip, and in the specific chip the specific bit's function is not used. (Example - a register (designed for the entire controller family) controls parameters for 2 USB channels, but the specific family member with a smaller-size package only has one USB channel bonded out.)

Regards, Naoum Gitnik.

topic Re: DDRMC_PHY02 Register Reserved Bits? in Vybrid Processors

DDRMC_PHY02 Register Reserved Bits?

Re: DDRMC_PHY02 Register Reserved Bits?