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    <title>Vybrid ProcessorsのトピックRe: USB Host DMA to internal SRAM - Data abort</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/453088#M5036</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Dirk,&lt;/P&gt;&lt;P&gt;DMA transfer can be interrupted due many reasons (bus error, incorrect descriptors,...). Please check DMAx_ES ans DMAx_ERR registers.&lt;/P&gt;&lt;P&gt;Theoretically:&lt;/P&gt;&lt;P&gt;SRAM and SDRAM has similar throughput (on NIC 64 b / 133-166MHz both). SRAM has significantly less latency. So here should not be the limitation.&lt;/P&gt;&lt;P&gt;Question is if some other master on NIC does need SRAM. Where is your program runs from? Please describe your use case (operating system or baremetal, which core,...).&lt;/P&gt;&lt;P&gt;/Jiri&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 04 Aug 2015 07:03:04 GMT</pubDate>
    <dc:creator>jiri-b36968</dc:creator>
    <dc:date>2015-08-04T07:03:04Z</dc:date>
    <item>
      <title>USB Host DMA to internal SRAM - Data abort</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/453087#M5035</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I use the freescale driver for USB Host to connect a mass storage device and read a file on it into the ddr memory which is attached to the vybrid.&lt;/P&gt;&lt;P&gt;This works well. Now I tried to stream the msd file content to the vybrids internal 512 kByte SRAM. If I do so the vybrid gets an data abort if the DMA&lt;/P&gt;&lt;P&gt;of the host controller starts to stream the msd file content to the internal SRAM.&lt;/P&gt;&lt;P&gt;Picture below shows my intenetion. While the USB Host DMA streams his transaction data into the internal SRAM, the Processor&lt;/P&gt;&lt;P&gt;can do any other stuff on the ddr memory without any interruption.&lt;/P&gt;&lt;P&gt;Why do I get an data abort if the dma starts his work?&lt;/P&gt;&lt;P&gt;Thanks for your help.&lt;/P&gt;&lt;P&gt; &lt;span class="lia-inline-image-display-wrapper" image-alt="SRAM_DMA.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/54166i399844A6E92B23F1/image-size/large?v=v2&amp;amp;px=999" role="button" title="SRAM_DMA.PNG" alt="SRAM_DMA.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Jul 2015 05:21:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/453087#M5035</guid>
      <dc:creator>dirkschmitt</dc:creator>
      <dc:date>2015-07-28T05:21:59Z</dc:date>
    </item>
    <item>
      <title>Re: USB Host DMA to internal SRAM - Data abort</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/453088#M5036</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Dirk,&lt;/P&gt;&lt;P&gt;DMA transfer can be interrupted due many reasons (bus error, incorrect descriptors,...). Please check DMAx_ES ans DMAx_ERR registers.&lt;/P&gt;&lt;P&gt;Theoretically:&lt;/P&gt;&lt;P&gt;SRAM and SDRAM has similar throughput (on NIC 64 b / 133-166MHz both). SRAM has significantly less latency. So here should not be the limitation.&lt;/P&gt;&lt;P&gt;Question is if some other master on NIC does need SRAM. Where is your program runs from? Please describe your use case (operating system or baremetal, which core,...).&lt;/P&gt;&lt;P&gt;/Jiri&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Aug 2015 07:03:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/453088#M5036</guid>
      <dc:creator>jiri-b36968</dc:creator>
      <dc:date>2015-08-04T07:03:04Z</dc:date>
    </item>
    <item>
      <title>This an automatic process.  We are marking this post as s...</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/1137933#M6121</link>
      <description>&lt;B&gt;This an automatic process.&lt;/B&gt;&lt;BR /&gt;&lt;BR /&gt;
We are marking this post as solved, due to the either low activity or any reply marked as correct.&lt;BR /&gt;&lt;BR /&gt;
If you have additional questions, please create a new post and reference to this closed post.&lt;BR /&gt;&lt;BR /&gt;
NXP Community!</description>
      <pubDate>Thu, 03 Sep 2020 17:41:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/USB-Host-DMA-to-internal-SRAM-Data-abort/m-p/1137933#M6121</guid>
      <dc:creator>CommunityBot</dc:creator>
      <dc:date>2020-09-03T17:41:46Z</dc:date>
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