SDR mode and DDR mode switch.

takashitakahash — Fri, 15 May 2015 09:16:37 GMT

Hi community.

VYBRIDRSERIESEC_Rev_7.PDF p58 "9.5.1 QuadSPI timing" description of "SDR mode"or"DDR mode",

but QSPIFlashROM by the command switches DDR and SDR.

This sheet described in the "SDR mode", "DDR mode" is bit7 of QuadSPI0_MCR register: will be set to "1" of DDR_EN?

Or refers to the mode of behavior when using the DDRRead/Write command and the SDRRead/Write command?

Re: SDR mode and DDR mode switch.

r8070z — Fri, 22 May 2015 04:42:11 GMT

Have a great day,

DDR Mode is enabled by setting the QSPI_MCR[DDR_EN].

The sampling register (QSPI_SMPR) should also be configured. When the serial flashes function in DDR mode the time for which the data is actually valid is smaller than half a clock cycle, it requires that we provide closely spaced sampling points.

Note that some flash vendors provide the DQS signal to which the read data is aligned in DDR mode (Spansion for example). When the DQS signal is used, the QSPI_MCR[DQS_EN] must be set.

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Vybrid ProcessorsのトピックRe: SDR mode and DDR mode switch.

SDR mode and DDR mode switch.

Re: SDR mode and DDR mode switch.