topic SPI slave mode receive register settings in Vybrid Processors

SPI slave mode receive register settings

MehmetAliIpin — Fri, 14 Feb 2014 09:40:00 GMT

Dear Sir/Madam,

I need to implement a SPI slave mode data reception from a SPI master for Vybrid VF3x. Since MQX does not support slave mode, I have to written the following SPI0_MCR and SPI0_CTAR register settings.

Of course, I tested it, but did not see any character in SPI0_POP register, or an error flag, or an interrupt flag is set.

I can send characters either DMA or SPI in master mode, but I can not receive in slave mode.

I have added my code segment below, I would be grateful, if you have a look and check if something is wrong or some extra registers are also controlled.

With my best regards,

Mehmet Ali Ipin

SPI0_MCR &= ~SPI_MCR_MDIS_MASK;

// Disable the module to change some bits..

#ifdef SPI_SLAVE_MODE

SPI0_MCR = SPI_MCR_HALT_MASK
	\|SPI_MCR_CLR_RXF_MASK
	\|SPI_MCR_CLR_TXF_MASK
	\|SPI_MCR_PCSIS(1)	//CS0 inactive state = high;
	\|SPI_MCR_ROOE_MASK	// Enable shift registers
	\|SPI_MCR_DCONF_MASK;

#else

SPI0_MCR = SPI_MCR_MSTR_MASK
	\|SPI_MCR_HALT_MASK
	\|SPI_MCR_CLR_RXF_MASK
	\|SPI_MCR_CLR_TXF_MASK
	\|SPI_MCR_PCSIS(1)	//CS0 inactive state = high;
	\|SPI_MCR_ROOE_MASK	// Enable shift registers
	\|SPI_MCR_DCONF_MASK;

#endif

SPI0_MCR \|= SPI_MCR_MDIS_MASK;
SPI0_CTAR0 = SPI_CTAR_FMSZ(7)	// 8 bit data will be received/transferred
		\|SPI_CTAR_DBR_MASK
		\|SPI_CTAR_PDT(7)
		\|SPI_CTAR_BR(2)
		\|SPI_CTAR_CPHA_MASK
		\|SPI_CTAR_CPOL_MASK;

Re: SPI slave mode receive register settings

MehmetAliIpin — Sat, 22 Feb 2014 10:59:40 GMT

Now, I can see the received characters in RX FIFO with these settings:

SPI0_MCR &= ~SPI_MCR_MDIS_MASK;

// Disable the module

SPI0_MCR = SPI_MCR_HALT_MASK| SPI_MCR_DOCNF_MASK // stop SPI

SPI0_RSER = 0; // disable interrupts

SPI0_RSER|= SPI_RSER_RFDF_RE_MASK; // Enable SPI receive int.

SPI0_SR = SPI_SR_EOQF_MASK|SPI_SR_TFUF_MASK|SPI_SR_TFFF_MASK|SPI_SR_RFOF_MASK|SPI_SR_RFDF_MASK;

I can see the correct values when I connect the SIN pin to either 3.3V or GND in RX FIFO.

Then I initialized the DMA without error with following codes:

DMA0_ERQ = DMA_ERQ_ERQ1_MASK; //channel 2

DMAMUX1_CHCFG1 = DMAMUX_CHCFG_ENBL_MASK

|DMAMUX_CHCFG_SOURCE(12) ; //Source 12 for SPI0 Rx

DMA0_TCD1_SADDR = (uint32_t)&SPI0_POPR; /* Set the Source Address */

/* Destination address */

DMA0_TCD1_DADDR = (uint32_t)(&dmaBuffer );

/* Source offset disabled */

DMA0_TCD1_SOFF = 0;

/* Source and Destination Modulo off, source and destination size 2 = 32 bits */

DMA0_TCD1_ATTR = DMA_ATTR_SMOD(0)|DMA_ATTR_SSIZE(2) | DMA_ATTR_DMOD(0)|DMA_ATTR_DSIZE(2);

/* Transfer 4 bytes per transaction */

DMA0_TCD1_NBYTES_MLNO = 4; // 16 bytes?

/* No adjust needed */

DMA0_TCD1_SLAST = 0;

/* Destination offset disabled */

DMA0_TCD1_DOFF = 4;

/* No link channel to channel, 1 transaction */

DMA0_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(16);

/* No adjustment to destination address */

DMA0_TCD1_DLASTSGA = 0;

DMA0_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(16);

DMA0_TCD1_CSR = DMA_CSR_DREQ_MASK|DMA_CSR_START_MASK; //One transfer only.

But I can not see anything in dmaBuffer.

What am I missing?

Thanks and best regards.

Re: Re: SPI slave mode receive register settings

juangutierrez — Thu, 06 Mar 2014 20:20:12 GMT

You can check the code in MQX regarding the DMA or also check the files attached. They are not granted to work but it can work as reference for you.