Vybrid ProcessorsのトピックSFlash configuration header

SFlash configuration header

tfe — Tue, 29 Sep 2015 06:36:41 GMT

We are working on a custom vybrid-based platform, and are attempting to boot from QSPI1(Spansion S25FL256S). The image we are attempting to boot have been tested and is known to work on the TWR-VF65GS10 kit using QSPI0.

From the Vybrid Manufacturing Tool, we extracted the following header which was contained it a pre-compiled image bundled with the tool.

------------------------- SFLASH CONFIG HEADER START -------------------------

Hold delay: 0 (disabled)

Half Speed Phase Selection: 0 (Select sampling at non-inverted clock)

Half Speed Delay: 0 (One clock cycle delay)

Chip Select hold time: 0

Chip Select setup time: 0

Serial Flash A1 size: 0x01000000 (16MB)

Serial Flash A2 size: 0

Serial Flash B1 size: 0x01000000 (16MB)

Serial Flash B2 size: 0

Serial Clock Frequency: 1 (60 MHz)

Mode of operation of serial Flash: 4 (Quad 4-bit data)

Serial Flash Port B selection: 0 (Port B is not used)

Dual Data Rate mode enable: 0 (DDR mode is disabled)

Data Strobe Signal enable in Serial Flash: 0 (Disable DQS)

Parallel Mode enable: 0 (Disable Parallel Mode in QSPI)

CS1 on Port A: 0 (Disable CS1 on Port A)

CS1 on Port B: 0 (Disable CS1 on Port B)

Full Speed Phase Selection: 0 (Select sampling at non-inverted clock)

Full Speed Delay Selection: 0 (One clock cycle delay)

DDR Sampling Point: 0

-------------------------- SFLASH CONFIG HEADER END --------------------------

We have attempted to change the "Serial Flash Port B selection" field to 1, set the size of A1 to 0x00 and B1 to 0x02000000, but unfortunately this does not work.

We have set our card to boot from fuses, and set the bootconfig appropriately. Probing the QSPI-flash chip shows that there is traffic between the MCU and chip upon boot.

Does anyone have any input?

Re: SFlash configuration header

karina_valencia — Mon, 05 Oct 2015 16:15:51 GMT

timesyssupport are you able to attend this case?

Re: SFlash configuration header

timesyssupport — Tue, 06 Oct 2015 19:01:59 GMT

Hello,

We are currently looking into this, and attempting to determine a cause. We will follow up when we have some insight.

Thank you,

Timesys Support

Re: SFlash configuration header

karina_valencia — Mon, 12 Oct 2015 17:20:57 GMT

timesyssupport do you have an update?

Re: SFlash configuration header

tfe — Tue, 13 Oct 2015 06:24:35 GMT

I eventually figured this out myself. Only a small modification was necessary:

------------------------- SFLASH CONFIG HEADER START -------------------------

Hold delay: 0 (disabled)

Half Speed Phase Selection: 0 (Select sampling at non-inverted clock)

Half Speed Delay: 0 (One clock cycle delay)

Chip Select hold time: 0

Chip Select setup time: 0

Serial Flash A1 size: 0x02000000 (32MB)

Serial Flash A2 size: 0

Serial Flash B1 size: 0

Serial Flash B2 size: 0

Serial Clock Frequency: 1 (60 MHz)

Mode of operation of serial Flash: 4 (Quad 4-bit data)

Serial Flash Port B selection: 0 (Port B is not used)

Dual Data Rate mode enable: 0 (DDR mode is disabled)

Data Strobe Signal enable in Serial Flash: 0 (Disable DQS)

Parallel Mode enable: 0 (Disable Parallel Mode in QSPI)

CS1 on Port A: 0 (Disable CS1 on Port A)

CS1 on Port B: 0 (Disable CS1 on Port B)

Full Speed Phase Selection: 0 (Select sampling at non-inverted clock)

Full Speed Delay Selection: 0 (One clock cycle delay)

DDR Sampling Point: 0

-------------------------- SFLASH CONFIG HEADER END --------------------------

Cheers