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    <title>Vybrid Processors中的主题 Re: 8-bit NAND interface</title>
    <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234013#M445</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Ioseph.&lt;/P&gt;&lt;P&gt;We have implemented NAND (in 8-bit mode) on an i.MX53 design.&amp;nbsp; Unfortunately the NFC controller in Vybrid is quite different to the 53.&amp;nbsp; &lt;/P&gt;&lt;P&gt;I'm sure it is something we are doing wrong, but it would be nice to know that Freescale (or someone else) has had it going in 8-bit mode.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Jun 2013 20:25:01 GMT</pubDate>
    <dc:creator>mnw</dc:creator>
    <dc:date>2013-06-25T20:25:01Z</dc:date>
    <item>
      <title>8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234011#M443</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have an 8-bit NAND part on a board and can't get an ID out of it.&amp;nbsp; The NAND part is the 8-bit version of the one on the tower board.&amp;nbsp; The only code change that I can see we need to do is ensure the BITWIDTH bit in the NFC_CFG register is not set.&lt;/P&gt;&lt;P&gt;Does anyone else have an experience with this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 22 Jun 2013 01:42:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234011#M443</guid>
      <dc:creator>mnw</dc:creator>
      <dc:date>2013-06-22T01:42:12Z</dc:date>
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    <item>
      <title>Re: 8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234012#M444</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I don't have experience on NAND but found this thread on this community &lt;A _jive_internal="true" href="https://community.nxp.com/thread/265412"&gt;https://community.freescale.com/thread/265412&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Perhaps if you look at the i.mx53 sw as reference it may help.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Jun 2013 17:59:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234012#M444</guid>
      <dc:creator>ioseph_martinez</dc:creator>
      <dc:date>2013-06-25T17:59:49Z</dc:date>
    </item>
    <item>
      <title>Re: 8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234013#M445</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Ioseph.&lt;/P&gt;&lt;P&gt;We have implemented NAND (in 8-bit mode) on an i.MX53 design.&amp;nbsp; Unfortunately the NFC controller in Vybrid is quite different to the 53.&amp;nbsp; &lt;/P&gt;&lt;P&gt;I'm sure it is something we are doing wrong, but it would be nice to know that Freescale (or someone else) has had it going in 8-bit mode.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Jun 2013 20:25:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234013#M445</guid>
      <dc:creator>mnw</dc:creator>
      <dc:date>2013-06-25T20:25:01Z</dc:date>
    </item>
    <item>
      <title>Re: 8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234014#M446</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You are right, the NFC in Vybrid is different from the i.MX family. I actually reviewed some material and seems to be the same controller used on Kinetis family. So let me check internally who with some experience on it can help.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Jun 2013 20:46:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234014#M446</guid>
      <dc:creator>ioseph_martinez</dc:creator>
      <dc:date>2013-06-26T20:46:22Z</dc:date>
    </item>
    <item>
      <title>Re: 8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234015#M447</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I got this info from a colleague, is how to use the one on the Tower board as a 8bit NAND:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;
&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;Steps to get TWR-VF600 16-bit to work on 8-bit:&lt;/SPAN&gt;&lt;/P&gt;
&lt;OL style="list-style-type: decimal;"&gt;
&lt;LI&gt;&lt;SPAN style="color: #1f497d;"&gt;1. IOMUX for NAND IO, set up&amp;nbsp; only 0-7. Command will set to lower byte, if send to high byte. The NAND device will not recognize any command send by the controller.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN style="color: #1f497d;"&gt;2. NAND_CFG, set to 8-bit for erase/program/read&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN style="color: #1f497d;"&gt;3. Spare bytes reduce to 32-bytes instead of 64-bytes; therefore, your HW ECC should set to 24-byte ECC.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="color: #1f497d;"&gt;What happen here is that 128MB of flash will be half of the size, the other half will not be used. When the controller read/write, it will be lower half of the byte.&lt;/SPAN&gt;&lt;/P&gt;
&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Comparing to what you are doing, I think would be good to check the following:&lt;/P&gt;&lt;P&gt;- can you try this on the tower board?&lt;/P&gt;&lt;P&gt;- is the NAND connected on your board to the lower lines? 0-7&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Jun 2013 18:23:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234015#M447</guid>
      <dc:creator>ioseph_martinez</dc:creator>
      <dc:date>2013-06-28T18:23:41Z</dc:date>
    </item>
    <item>
      <title>Re: 8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234016#M448</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;I did not try this, but was able to get the flash part responding to the ID command using the latest MQX beta.&lt;/P&gt;&lt;P&gt;The whole test is not working, but there may be other software reasons for that.&amp;nbsp; I do have a couple of questions about some strange things I'm seeing:&lt;/P&gt;&lt;P&gt;1. The MQX and u-Boot code is very different when comparing how the I/O lines are setup. u-Boot enables both the input and output buffer (OBE and IBE bits),but MQX only enables IBE.&amp;nbsp; Do you have any comments or recommendations on which software to follow?&lt;/P&gt;&lt;P&gt;2. When analysing the ID Read sequence,&amp;nbsp; I see the CE# line cycle for every bus cycle.&amp;nbsp; The timing diagram for the Micron NAND shows that CE# should stay low for the whole operation.&amp;nbsp; Is there a setting in the controller to fix this?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 05 Jul 2013 06:28:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234016#M448</guid>
      <dc:creator>mnw</dc:creator>
      <dc:date>2013-07-05T06:28:36Z</dc:date>
    </item>
    <item>
      <title>Re: 8-bit NAND interface</title>
      <link>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234017#M449</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Martin,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Maybe better if you post a this questions on a different thread?&lt;/P&gt;&lt;P&gt;Since the topic is a bit different now...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ioseph&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 09 Jul 2013 14:43:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Vybrid-Processors/8-bit-NAND-interface/m-p/234017#M449</guid>
      <dc:creator>ioseph_martinez</dc:creator>
      <dc:date>2013-07-09T14:43:48Z</dc:date>
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